SPRSP93 November   2024 F29H850TU , F29H859TU-Q1

ADVANCE INFORMATION  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
    1. 3.1 Functional Block Diagram
  5. 4 Device Comparison
    1. 4.1 Related Products
  6. 5 Pin Configuration and Functions
    1. 5.1 Pin Diagrams
    2. 5.2 Pin Attributes
    3. 5.3 Signal Descriptions
      1. 5.3.1 Analog Signals
      2. 5.3.2 Digital Signals
      3. 5.3.3 Power and Ground
      4. 5.3.4 Test, JTAG, and Reset
    4. 5.4 Pins With Internal Pullup and Pulldown
    5. 5.5 Pin Multiplexing
      1. 5.5.1 GPIO Muxed Pins
    6. 5.6 Connections for Unused Pins
  7. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  F29H85x ESD Ratings – Commercial
    3. 6.3  F29H85x ESD Ratings – Automotive
    4. 6.4  F29P58x ESD Ratings – Commercial
    5. 6.5  F29P58x ESD Ratings – Automotive
    6. 6.6  Recommended Operating Conditions
    7. 6.7  Power Consumption Summary
      1. 6.7.1 System Current Consumption VREG Enabled
      2. 6.7.2 System Current Consumption VREG Disable - External Supply
      3. 6.7.3 Operating Mode Test Description
      4. 6.7.4 Reducing Current Consumption
        1. 6.7.4.1 Typical Current Reduction per Disabled Peripheral
    8. 6.8  Electrical Characteristics
    9. 6.9  Thermal Resistance Characteristics for ZEX Package
    10. 6.10 Thermal Resistance Characteristics for PTS Package
    11. 6.11 Thermal Resistance Characteristics for RFS Package
    12. 6.12 Thermal Resistance Characteristics for PZS Package
    13. 6.13 Thermal Design Considerations
    14. 6.14 System
      1. 6.14.1  Power Management Module (PMM)
        1. 6.14.1.1 Introduction
        2. 6.14.1.2 Overview
          1. 6.14.1.2.1 Power Rail Monitors
            1. 6.14.1.2.1.1 I/O POR (Power-On Reset) Monitor
            2. 6.14.1.2.1.2 I/O BOR (Brown-Out Reset) Monitor
            3. 6.14.1.2.1.3 VDD POR (Power-On Reset) Monitor
          2. 6.14.1.2.2 External Supervisor Usage
          3. 6.14.1.2.3 Delay Blocks
          4. 6.14.1.2.4 Internal 1.2-V LDO Voltage Regulator (VREG)
          5. 6.14.1.2.5 VREGENZ
        3. 6.14.1.3 External Components
          1. 6.14.1.3.1 Decoupling Capacitors
            1. 6.14.1.3.1.1 VDDIO Decoupling
            2. 6.14.1.3.1.2 VDD Decoupling
        4. 6.14.1.4 Power Sequencing
          1. 6.14.1.4.1 Supply Pins Ganging
          2. 6.14.1.4.2 Signal Pins Power Sequence
          3. 6.14.1.4.3 Supply Pins Power Sequence
            1. 6.14.1.4.3.1 External VREG/VDD Mode Sequence
            2. 6.14.1.4.3.2 Internal VREG/VDD Mode Sequence
            3. 6.14.1.4.3.3 Supply Sequencing Summary and Effects of Violations
            4. 6.14.1.4.3.4 Supply Slew Rate
        5. 6.14.1.5 Power Management Module Electrical Data and Timing
          1. 6.14.1.5.1 Power Management Module Operating Conditions
          2. 6.14.1.5.2 Power Management Module Characteristics
      2. 6.14.2  Reset Timing
        1. 6.14.2.1 Reset Sources
        2. 6.14.2.2 Reset Electrical Data and Timing
          1. 6.14.2.2.1 Reset XRSn Timing Requirements
          2. 6.14.2.2.2 Reset XRSn Switching Characteristics
          3. 6.14.2.2.3 Reset Timing Diagrams
      3. 6.14.3  Clock Specifications
        1. 6.14.3.1 Clock Sources
        2. 6.14.3.2 Clock Frequencies, Requirements, and Characteristics
          1. 6.14.3.2.1 Input Clock Frequency and Timing Requirements, PLL Lock Times
            1. 6.14.3.2.1.1 Input Clock Frequency
            2. 6.14.3.2.1.2 XTAL Oscillator Characteristics
            3. 6.14.3.2.1.3 X1 Input Level Characteristics When Using an External Clock Source Not a Crystal
            4. 6.14.3.2.1.4 X1 Timing Requirements
            5. 6.14.3.2.1.5 AUXCLKIN Timing Requirements
            6. 6.14.3.2.1.6 APLL Characteristics
            7. 6.14.3.2.1.7 XCLKOUT Switching Characteristics PLL Bypassed or Enabled
        3. 6.14.3.3 Input Clocks
        4. 6.14.3.4 XTAL Oscillator
          1. 6.14.3.4.1 Introduction
          2. 6.14.3.4.2 Overview
            1. 6.14.3.4.2.1 Electrical Oscillator
              1. 6.14.3.4.2.1.1 Modes of Operation
                1. 6.14.3.4.2.1.1.1 Crystal Mode of Operation
                2. 6.14.3.4.2.1.1.2 Single-Ended Mode of Operation
              2. 6.14.3.4.2.1.2 XTAL Output on XCLKOUT
            2. 6.14.3.4.2.2 Quartz Crystal
            3. 6.14.3.4.2.3 GPIO Modes of Operation
          3. 6.14.3.4.3 Functional Operation
            1. 6.14.3.4.3.1 ESR – Effective Series Resistance
            2. 6.14.3.4.3.2 Rneg – Negative Resistance
            3. 6.14.3.4.3.3 Start-up Time
            4. 6.14.3.4.3.4 DL – Drive Level
          4. 6.14.3.4.4 How to Choose a Crystal
          5. 6.14.3.4.5 Testing
          6. 6.14.3.4.6 Common Problems and Debug Tips
          7. 6.14.3.4.7 Crystal Oscillator Specifications
            1. 6.14.3.4.7.1 Crystal Oscillator Electrical Characteristics
            2. 6.14.3.4.7.2 Crystal Equivalent Series Resistance (ESR) Requirements
            3. 6.14.3.4.7.3 Crystal Oscillator Parameters
            4. 6.14.3.4.7.4 Crystal Oscillator Electrical Characteristics
        5. 6.14.3.5 Internal Oscillators
          1. 6.14.3.5.1 INTOSC Characteristics
      4. 6.14.4  Flash Parameters
        1. 6.14.4.1 Flash Parameters 
      5. 6.14.5  Memory Subsystem (MEMSS)
        1. 6.14.5.1 Introduction
        2. 6.14.5.2 Features
        3. 6.14.5.3 RAM Specifications
      6. 6.14.6  Debug/JTAG
        1. 6.14.6.1 JTAG Electrical Data and Timing
          1. 6.14.6.1.1 DEBUGSS Timing Requirements
          2. 6.14.6.1.2 DEBUGSS Switching Characteristics
          3. 6.14.6.1.3 JTAG Timing Diagram
          4. 6.14.6.1.4 SWD Timing Diagram
      7. 6.14.7  GPIO Electrical Data and Timing
        1. 6.14.7.1 GPIO – Output Timing
          1. 6.14.7.1.1 General-Purpose Output Switching Characteristics
          2. 6.14.7.1.2 General-Purpose Output Timing Diagram
        2. 6.14.7.2 GPIO – Input Timing
          1. 6.14.7.2.1 General-Purpose Input Timing Requirements
          2. 6.14.7.2.2 Sampling Mode
        3. 6.14.7.3 Sampling Window Width for Input Signals
      8. 6.14.8  Real-Time Direct Memory Access (RTDMA)
        1. 6.14.8.1 Introduction
          1. 6.14.8.1.1 Features
          2. 6.14.8.1.2 Block Diagram
      9. 6.14.9  Low-Power Modes
        1. 6.14.9.1 Clock-Gating Low-Power Modes
        2. 6.14.9.2 Low-Power Mode Wake-up Timing
          1. 6.14.9.2.1 IDLE Mode Timing Requirements
          2. 6.14.9.2.2 IDLE Mode Switching Characteristics
          3. 6.14.9.2.3 IDLE Entry and Exit Timing Diagram
          4. 6.14.9.2.4 STANDBY Mode Timing Requirements
          5. 6.14.9.2.5 STANDBY Mode Switching Characteristics
          6. 6.14.9.2.6 STANDBY Entry and Exit Timing Diagram
      10. 6.14.10 External Memory Interface (EMIF)
        1. 6.14.10.1 Asynchronous Memory Support
        2. 6.14.10.2 Synchronous DRAM Support
        3. 6.14.10.3 EMIF Electrical Data and Timing
          1. 6.14.10.3.1 EMIF Synchronous Memory Timing Requirements
          2. 6.14.10.3.2 EMIF Synchronous Memory Switching Characteristics
          3. 6.14.10.3.3 EMIF Synchronous Memory Timing Diagrams
          4. 6.14.10.3.4 EMIF Asynchronous Memory Timing Requirements
          5. 6.14.10.3.5 EMIF Asynchronous Memory Switching Characteristics
          6. 6.14.10.3.6 EMIF Asynchronous Memory Timing Diagrams
    15. 6.15 C29x Analog Peripherals
      1. 6.15.1 Analog Subsystem
        1. 6.15.1.1 Features
        2. 6.15.1.2 Block Diagram
        3. 6.15.1.3 Analog Pin Connections
      2. 6.15.2 Analog-to-Digital Converter (ADC)
        1. 6.15.2.1 ADC Configurability
          1. 6.15.2.1.1 Signal Mode
        2. 6.15.2.2 ADC Electrical Data and Timing
          1. 6.15.2.2.1  ADC Operating Conditions 12-bit Single-Ended
          2. 6.15.2.2.2  ADC Operating Conditions 12-bit Differential
          3. 6.15.2.2.3  ADC Operating Conditions 16-bit Single-Ended
          4. 6.15.2.2.4  ADC Operating Conditions 16-bit Differential
          5. 6.15.2.2.5  ADC Timing Requirements
          6. 6.15.2.2.6  ADC Characteristics 12-bit Single-Ended
          7. 6.15.2.2.7  ADC Characteristics 12-bit Differential
          8. 6.15.2.2.8  ADC Characteristics 16-bit Single-Ended
          9. 6.15.2.2.9  ADC Characteristics 16-bit Differential
          10. 6.15.2.2.10 ADC INL and DNL
          11. 6.15.2.2.11 ADC Input Model Models
          12. 6.15.2.2.12 ADC Timing Diagrams
      3. 6.15.3 Temperature Sensor
        1. 6.15.3.1 Temperature Sensor Electrical Data and Timing
          1. 6.15.3.1.1 Temperature Sensor Characteristics
      4. 6.15.4 Comparator Subsystem (CMPSS)
        1. 6.15.4.1 CMPSS Connectivity Diagram
        2. 6.15.4.2 Block Diagram
        3. 6.15.4.3 CMPSS Electrical Data and Timing
          1. 6.15.4.3.1 Comparator Electrical Characteristics
          2.        CMPSS Comparator Input Referred Offset and Hysteresis
          3. 6.15.4.3.2 CMPSS DAC Static Electrical Characteristics
          4. 6.15.4.3.3 CMPSS Illustrative Graphs
      5. 6.15.5 Buffered Digital-to-Analog Converter (DAC)
        1. 6.15.5.1 Buffered DAC Electrical Data and Timing
          1. 6.15.5.1.1 Buffered DAC Operating Conditions
          2. 6.15.5.1.2 Buffered DAC Electrical Characteristics
    16. 6.16 C29x Control Peripherals
      1. 6.16.1 Enhanced Capture (eCAP)
        1. 6.16.1.1 eCAP Block Diagram
        2. 6.16.1.2 eCAP Synchronization
        3. 6.16.1.3 eCAP Electrical Data and Timing
          1. 6.16.1.3.1 eCAP Timing Requirements
          2. 6.16.1.3.2 eCAP Switching Characteristics
      2. 6.16.2 High-Resolution Capture (HRCAP)
        1. 6.16.2.1 eCAP and HRCAP Block Diagram
        2. 6.16.2.2 HRCAP Electrical Data and Timing
          1. 6.16.2.2.1 HRCAP Switching Characteristics
          2. 6.16.2.2.2 HRCAP Figure and Graph
      3. 6.16.3 Enhanced Pulse Width Modulator (ePWM)
        1. 6.16.3.1 Control Peripherals Synchronization
        2. 6.16.3.2 ePWM Electrical Data and Timing
          1. 6.16.3.2.1 ePWM Timing Requirements
          2. 6.16.3.2.2 ePWM Switching Characteristics
          3. 6.16.3.2.3 Trip-Zone Input Timing
            1. 6.16.3.2.3.1 PWM Hi-Z Characteristics Timing Diagram
      4. 6.16.4 External ADC Start-of-Conversion Electrical Data and Timing
        1. 6.16.4.1 External ADC Start-of-Conversion Switching Characteristics
        2. 6.16.4.2 ADCSOCAO or ADCSOCBO Timing Diagram
      5. 6.16.5 High-Resolution Pulse Width Modulator (HRPWM)
        1. 6.16.5.1 HRPWM Electrical Data and Timing
          1. 6.16.5.1.1 High-Resolution PWM Characteristics
      6. 6.16.6 Enhanced Quadrature Encoder Pulse (eQEP)
        1. 6.16.6.1 eQEP Electrical Data and Timing
          1. 6.16.6.1.1 eQEP Timing Requirements
          2. 6.16.6.1.2 eCAP Switching Characteristics
      7. 6.16.7 Sigma-Delta Filter Module (SDFM)
        1. 6.16.7.1 SDFM Electrical Data and Timing
          1. 6.16.7.1.1 SDFM Electrical Data and Timing (Synchronized GPIO)
          2. 6.16.7.1.2 SDFM Electrical Data and Timing (Using ASYNC)
            1. 6.16.7.1.2.1 SDFM Timing Requirements When Using Asynchronous GPIO ASYNC Option
            2. 6.16.7.1.2.2 SDFM Timing Requirements When Using Synchronous GPIO SYNC Option
          3. 6.16.7.1.3 SDFM Timing Diagram
    17. 6.17 C29x Communications Peripherals
      1. 6.17.1 Modular Controller Area Network (MCAN)
      2. 6.17.2 Fast Serial Interface (FSI)
        1. 6.17.2.1 FSI Transmitter
          1. 6.17.2.1.1 FSITX Electrical Data and Timing
            1. 6.17.2.1.1.1 FSITX Switching Characteristics
            2. 6.17.2.1.1.2 FSITX Timings
        2. 6.17.2.2 FSI Receiver
          1. 6.17.2.2.1 FSIRX Electrical Data and Timing
            1. 6.17.2.2.1.1 FSIRX Timing Requirements
            2. 6.17.2.2.1.2 FSIRX Switching Characteristics
            3. 6.17.2.2.1.3 FSIRX Timings
        3. 6.17.2.3 FSI SPI Compatibility Mode
          1. 6.17.2.3.1 FSITX SPI Signaling Mode Electrical Data and Timing
            1. 6.17.2.3.1.1 FSITX SPI Signaling Mode Switching Characteristics
            2. 6.17.2.3.1.2 FSITX SPI Signaling Mode Timings
      3. 6.17.3 Inter-Integrated Circuit (I2C)
        1. 6.17.3.1 I2C Electrical Data and Timing
          1. 6.17.3.1.1 I2C Timing Requirements
          2. 6.17.3.1.2 I2C Switching Characteristics
          3. 6.17.3.1.3 I2C Timing Diagram
      4. 6.17.4 Power Management Bus (PMBus) Interface
        1. 6.17.4.1 PMBus Electrical Data and Timing
          1. 6.17.4.1.1 PMBus Electrical Characteristics
          2. 6.17.4.1.2 PMBus Fast Plus Mode Switching Characteristics
          3. 6.17.4.1.3 PMBus Fast Mode Switching Characteristics
          4. 6.17.4.1.4 PMBus Standard Mode Switching Characteristics
      5. 6.17.5 Serial Peripheral Interface (SPI)
        1. 6.17.5.1 SPI Controller Mode Timings
          1. 6.17.5.1.1 SPI Controller Mode Switching Characteristics Clock Phase 0
          2. 6.17.5.1.2 SPI Controller Mode Switching Characteristics Clock Phase 1
          3. 6.17.5.1.3 SPI Controller Mode Timing Requirements
          4. 6.17.5.1.4 SPI Controller Mode Timing Diagrams
        2. 6.17.5.2 SPI Peripheral Mode Timings
          1. 6.17.5.2.1 SPI Peripheral Mode Switching Characteristics
          2. 6.17.5.2.2 SPI Peripheral Mode Timing Requirements
          3. 6.17.5.2.3 SPI Peripheral Mode Timing Diagrams
      6. 6.17.6 Single Edge Nibble Transmission (SENT)
        1. 6.17.6.1 Introduction
        2. 6.17.6.2 Features
      7. 6.17.7 Local Interconnect Network (LIN)
      8. 6.17.8 EtherCAT SubordinateDevice Controller (ESC)
        1. 6.17.8.1 ESC Features
        2. 6.17.8.2 ESC Subsystem Integrated Features
        3. 6.17.8.3 EtherCAT IP Block Diagram
        4. 6.17.8.4 EtherCAT Electrical Data and Timing
          1. 6.17.8.4.1 EtherCAT Timing Requirements
          2. 6.17.8.4.2 EtherCAT Switching Characteristics
          3. 6.17.8.4.3 EtherCAT Timing Diagrams
      9. 6.17.9 Universal Asynchronous Receiver-Transmitter (UART)
  8. 7 Detailed Description
    1. 7.1  Overview
    2. 7.2  Functional Block Diagram
    3. 7.3  Error Signaling Module (ESM_C29)
      1. 7.3.1 Introduction
      2. 7.3.2 ESM Subsystem
      3. 7.3.3 System ESM
    4. 7.4  Error Aggregator
      1. 7.4.1 Error Aggregator Modules
      2. 7.4.2 Error Aggregator Interface
    5. 7.5  Memory
      1. 7.5.1 C29x Memory Map
      2. 7.5.2 Flash Memory Map
        1. 7.5.2.1 Flash MAIN Region Address Map (F29H85x, 4MB)
        2. 7.5.2.2 Flash MAIN Region Address Map (F29H85x, 2MB)
        3. 7.5.2.3 Flash MAIN Region Address Map (F29P58x, 4MB)
        4. 7.5.2.4 Flash MAIN Region Address Map (F29P58x, 2MB)
        5. 7.5.2.5 Flash MAIN Region Address MAP (F29P58x, 1MB)
        6. 7.5.2.6 Flash Data Bank Address Map
        7. 7.5.2.7 Flash BANKMGMT Region Address Map
        8. 7.5.2.8 Flash SECCFG Region Address Map
      3. 7.5.3 Peripheral Registers Memory Map
    6. 7.6  Identification
    7. 7.7  Boot ROM
      1. 7.7.1 Device Boot Sequence
      2. 7.7.2 Device Boot Modes
        1. 7.7.2.1 Default Boot Modes
        2. 7.7.2.2 Custom Boot Modes
      3. 7.7.3 Device Boot Configurations
        1. 7.7.3.1 Configuring Boot Mode Pins
        2. 7.7.3.2 Configuring Boot Mode Table Options
      4. 7.7.4 Device Boot Flow Diagrams
        1. 7.7.4.1 Device Boot Flow
        2. 7.7.4.2 CPU1 Boot Flow
        3. 7.7.4.3 Emulation Boot Flow
        4. 7.7.4.4 Stand-alone Boot Flow
      5. 7.7.5 GPIO Assignments
    8. 7.8  Security Modules and Cryptographic Accelerators
      1. 7.8.1 Security Modules
        1. 7.8.1.1 Hardware Security Module (HSM)
        2. 7.8.1.2 Cryptographic Accelerators
      2. 7.8.2 Safety and Security Unit (SSU)
        1. 7.8.2.1 System View
    9. 7.9  C29x Subsystem
      1. 7.9.1 C29 CPU Architecture
      2. 7.9.2 Peripheral Interrupt Priority and Expansion (PIPE)
        1. 7.9.2.1 Introduction
          1. 7.9.2.1.1 Features
          2. 7.9.2.1.2 Interrupt Concepts
        2. 7.9.2.2 Interrupt Architecture
          1. 7.9.2.2.1 Dynamic Priority Arbitration Block
          2. 7.9.2.2.2 Post Processing Block
          3. 7.9.2.2.3 Memory Mapped Registers
        3. 7.9.2.3 Interrupt Propagation
      3. 7.9.3 Data Logging and Trace (DLT)
        1. 7.9.3.1 Introduction
          1. 7.9.3.1.1 Features
            1. 7.9.3.1.1.1 Block Diagram
      4. 7.9.4 Waveform Analyzer Diagnostics (WADI)
        1. 7.9.4.1 WADI Overview
          1. 7.9.4.1.1 Features
          2. 7.9.4.1.2 Block Diagram
          3. 7.9.4.1.3 Description
      5. 7.9.5 Embedded Real-Time Analysis and Diagnostic (ERAD)
      6. 7.9.6 Inter-Processor Communications (IPC)
        1. 7.9.6.1 Introduction
      7. 7.9.7 Watchdog
      8. 7.9.8 Dual-Clock Comparator (DCC)
        1. 7.9.8.1 Features
        2. 7.9.8.2 Mapping of DCCx Clock Source Inputs
      9. 7.9.9 Configurable Logic Block (CLB)
    10. 7.10 Lockstep Compare Module (LCM)
  9. 8 Applications, Implementation, and Layout
    1. 8.1 Reference Design
  10. 9 Device and Documentation Support
    1. 9.1 Device Nomenclature
    2. 9.2 Markings
    3. 9.3 Tools and Software
    4. 9.4 Documentation Support
    5. 9.5 Support Resources
    6. 9.6 Trademarks
    7. 9.7 Electrostatic Discharge Caution
    8. 9.8 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information
    1. 11.1 Packaging Information
    2.     TRAY

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • PZS|100
  • PTS|176
  • RFS|144
  • ZEX|256
Thermal pad, mechanical data (Package|Pins)
Orderable Information

5.3.1 Analog Signals

Table 5-2 Analog Signals
SIGNAL NAME PIN TYPE DESCRIPTION GPIO 256 ZEX 176 PTS 144 RFS 100 PZS
A0 I ADC-A Input 0 R1 44 36 25
A1 I ADC-A Input 1 P1 43 35 24
A2 I ADC-A Input 2 M1 36 28
A3 I ADC-A Input 3 M2 35 27
A4 I ADC-A Input 4 L2 32 24
A5 I ADC-A Input 5 L1 31 23
A6 I ADC-A Input 6 224 L5 26 18 13
A7 I ADC-A Input 7 225 K5 25 17 12
A8 I ADC-A Input 8 226 H4 22 16
A9 I ADC-A Input 9 227 H3 21
A10 I ADC-A Input 10 228 G3 18
A11 I ADC-A Input 11 229 G4 17
A12 I ADC-A Input 12 K2
A13 I ADC-A Input 13 K1
A14 I ADC-A Input 14 M3 40 32 21
A15 I ADC-A Input 15 M4 39 31 20
A24 I ADC-A Input 24 P3 49 41 30
A25 I ADC-A Input 25 P4 50 42 31
A26 I ADC-A Input 26 T5 59 51
A27 I ADC-A Input 27 T6 60 52
A28 I ADC-A Input 28 246 P11 67 56 38
A29 I ADC-A Input 29 247 R11 68 57 39
A30 I ADC-A Input 30 248 P13 73 62
A31 I ADC-A Input 31 249 N13 74 63
AIO160 I Analog Pin Used For Digital Input 160 R1 44 36 25
AIO161 I Analog Pin Used For Digital Input 161 P1 43 35 24
AIO162 I Analog Pin Used For Digital Input 162 M1 36 28
AIO163 I Analog Pin Used For Digital Input 163 M2 35 27
AIO164 I Analog Pin Used For Digital Input 164 L2 32 24
AIO165 I Analog Pin Used For Digital Input 165 L1 31 23
AIO166 I Analog Pin Used For Digital Input 166 K2
AIO167 I Analog Pin Used For Digital Input 167 K1
AIO168 I Analog Pin Used For Digital Input 168 M3 40 32 21
AIO169 I Analog Pin Used For Digital Input 169 M4 39 31 20
AIO170 I Analog Pin Used For Digital Input 170 P2 42 34 23
AIO171 I Analog Pin Used For Digital Input 171 N3 41 33 22
AIO172 I Analog Pin Used For Digital Input 172 L4 34 26 17
AIO173 I Analog Pin Used For Digital Input 173 L3 33 25 16
AIO174 I Analog Pin Used For Digital Input 174 K4 30 22
AIO175 I Analog Pin Used For Digital Input 175 K3 29 21
AIO176 I Analog Pin Used For Digital Input 176 J2
AIO177 I Analog Pin Used For Digital Input 177 J1
AIO178 I Analog Pin Used For Digital Input 178 J4
AIO179 I Analog Pin Used For Digital Input 179 J3
AIO180 I Analog Pin Used For Digital Input 180 R2 45 37 26
AIO181 I Analog Pin Used For Digital Input 181 T2 46 38 27
AIO182 I Analog Pin Used For Digital Input 182 N4 51 43
AIO183 I Analog Pin Used For Digital Input 183 M5 52 44
AIO184 I Analog Pin Used For Digital Input 184 P5 55 47
AIO185 I Analog Pin Used For Digital Input 185 N5 56 48
AIO186 I Analog Pin Used For Digital Input 186 N8
AIO187 I Analog Pin Used For Digital Input 187 P8
AIO188 I Analog Pin Used For Digital Input 188 R8
AIO189 I Analog Pin Used For Digital Input 189 T8
AIO190 I Analog Pin Used For Digital Input 190 N7
AIO191 I Analog Pin Used For Digital Input 191 P7
AIO192 I Analog Pin Used For Digital Input 192 R3 47 39 28
AIO193 I Analog Pin Used For Digital Input 193 T3 48 40 29
AIO194 I Analog Pin Used For Digital Input 194 R5 57 49 34
AIO195 I Analog Pin Used For Digital Input 195 R6 58 50 35
AIO196 I Analog Pin Used For Digital Input 196 N6
AIO197 I Analog Pin Used For Digital Input 197 P6
AIO198 I Analog Pin Used For Digital Input 198 M7
AIO199 I Analog Pin Used For Digital Input 199 M6
AIO200 I Analog Pin Used For Digital Input 200 R7
AIO201 I Analog Pin Used For Digital Input 201 T7
AIO202 I Analog Pin Used For Digital Input 202 P3 49 41 30
AIO203 I Analog Pin Used For Digital Input 203 P4 50 42 31
AIO204 I Analog Pin Used For Digital Input 204 T5 59 51
AIO205 I Analog Pin Used For Digital Input 205 T6 60 52
AIO206 I Analog Pin Used For Digital Input 206 T10
AIO207 I Analog Pin Used For Digital Input 207 T9
AIO208 I Analog Pin Used For Digital Input 208 R10
AIO209 I Analog Pin Used For Digital Input 209 R9
AIO210 I Analog Pin Used For Digital Input 210 P9
AIO211 I Analog Pin Used For Digital Input 211 N9
AIO212 I Analog Pin Used For Digital Input 212 P10
AIO213 I Analog Pin Used For Digital Input 213 T11
B0 I ADC-B Input 0 P2 42 34 23
B1 I ADC-B Input 1 N3 41 33 22
B2 I ADC-B Input 2 L4 34 26 17
B3 I ADC-B Input 3 L3 33 25 16
B4 I ADC-B Input 4 K4 30 22
B5 I ADC-B Input 5 K3 29 21
B6 I ADC-B Input 6 230 J5 24
B7 I ADC-B Input 7 231 H5 23
B8 I ADC-B Input 8 232 H2 20 15 11
B9 I ADC-B Input 9 233 H1 19 14 10
B10 I ADC-B Input 10 234 G2 16 13
B11 I ADC-B Input 11 235 G1 15 12
B12 I ADC-B Input 12 J2
B13 I ADC-B Input 13 J1
B14 I ADC-B Input 14 M3 40 32 21
B15 I ADC-B Input 15 M4 39 31 20
B16 I ADC-B Input 16 J4
B17 I ADC-B Input 17 J3
B24 I ADC-B Input 24 R3 47 39 28
B25 I ADC-B Input 25 T3 48 40 29
B26 I ADC-B Input 26 R5 57 49 34
B27 I ADC-B Input 27 R6 58 50 35
B28 I ADC-B Input 28 240 N10 65
B29 I ADC-B Input 29 241 N11 66 55
B30 I ADC-B Input 30 242 T12 71 60
B31 I ADC-B Input 31 243 R12 72 61
C0 I ADC-C Input 0 R2 45 37 26
C1 I ADC-C Input 1 T2 46 38 27
C2 I ADC-C Input 2 N4 51 43
C3 I ADC-C Input 3 M5 52 44
C4 I ADC-C Input 4 P5 55 47
C5 I ADC-C Input 5 N5 56 48
C6 I ADC-C Input 6 236 M8 63
C7 I ADC-C Input 7 237 M9 64
C8 I ADC-C Input 8 238 N12 69 58 40
C9 I ADC-C Input 9 239 P12 70 59 41
C10 I ADC-C Input 10 N8
C11 I ADC-C Input 11 P8
C12 I ADC-C Input 12 R8
C13 I ADC-C Input 13 T8
C14 I ADC-C Input 14 M3 40 32 21
C15 I ADC-C Input 15 M4 39 31 20
C16 I ADC-C Input 16 N7
C17 I ADC-C Input 17 P7
C24 I ADC-C Input 24 R1 44 36 25
C25 I ADC-C Input 25 P1 43 35 24
C26 I ADC-C Input 26 P2 42 34 23
C27 I ADC-C Input 27 N3 41 33 22
C28 I ADC-C Input 28 244 R13 75
C29 I ADC-C Input 29 245 T13 76
C30 I ADC-C Input 30 T10
C31 I ADC-C Input 31 T9
CMP1_HN0 I CMPSS-1 High Comparator Negative Input 0 L1 31 23
CMP1_HN1 I CMPSS-1 High Comparator Negative Input 1 M2 35 27
CMP1_HP0 I CMPSS-1 High Comparator Positive Input 0 L2 32 24
CMP1_HP1 I CMPSS-1 High Comparator Positive Input 1 M1 36 28
CMP1_HP2 I CMPSS-1 High Comparator Positive Input 2 M2 35 27
CMP1_HP3 I CMPSS-1 High Comparator Positive Input 3 L3 33 25 16
CMP1_HP4 I CMPSS-1 High Comparator Positive Input 4 242 T12 71 60
CMP1_HP5 I CMPSS-1 High Comparator Positive Input 5 K2
CMP1_LN0 I CMPSS-1 Low Comparator Negative Input 0 L1 31 23
CMP1_LN1 I CMPSS-1 Low Comparator Negative Input 1 M2 35 27
CMP1_LP0 I CMPSS-1 Low Comparator Positive Input 0 L2 32 24
CMP1_LP1 I CMPSS-1 Low Comparator Positive Input 1 M1 36 28
CMP1_LP2 I CMPSS-1 Low Comparator Positive Input 2 M2 35 27
CMP1_LP3 I CMPSS-1 Low Comparator Positive Input 3 L3 33 25 16
CMP1_LP4 I CMPSS-1 Low Comparator Positive Input 4 242 T12 71 60
CMP1_LP5 I CMPSS-1 Low Comparator Positive Input 5 K2
CMP2_HN0 I CMPSS-2 High Comparator Negative Input 0 225 K5 25 17 12
CMP2_HN1 I CMPSS-2 High Comparator Negative Input 1 L2 32 24
CMP2_HP0 I CMPSS-2 High Comparator Positive Input 0 224 L5 26 18 13
CMP2_HP1 I CMPSS-2 High Comparator Positive Input 1 T10
CMP2_HP2 I CMPSS-2 High Comparator Positive Input 2 T9
CMP2_HP3 I CMPSS-2 High Comparator Positive Input 3 M6
CMP2_HP4 I CMPSS-2 High Comparator Positive Input 4 243 R12 72 61
CMP2_HP5 I CMPSS-2 High Comparator Positive Input 5 K1
CMP2_LN0 I CMPSS-2 Low Comparator Negative Input 0 225 K5 25 17 12
CMP2_LN1 I CMPSS-2 Low Comparator Negative Input 1 L2 32 24
CMP2_LP0 I CMPSS-2 Low Comparator Positive Input 0 224 L5 26 18 13
CMP2_LP1 I CMPSS-2 Low Comparator Positive Input 1 T10
CMP2_LP2 I CMPSS-2 Low Comparator Positive Input 2 T9
CMP2_LP3 I CMPSS-2 Low Comparator Positive Input 3 M6
CMP2_LP4 I CMPSS-2 Low Comparator Positive Input 4 243 R12 72 61
CMP2_LP5 I CMPSS-2 Low Comparator Positive Input 5 K1
CMP3_HN0 I CMPSS-3 High Comparator Negative Input 0 L3 33 25 16
CMP3_HN1 I CMPSS-3 High Comparator Negative Input 1 K3 29 21
CMP3_HP2 I CMPSS-3 High Comparator Positive Input 2 N3 41 33 22
CMP3_HP4 I CMPSS-3 High Comparator Positive Input 4 T5 59 51
CMP3_LN0 I CMPSS-3 Low Comparator Negative Input 0 L3 33 25 16
CMP3_LN1 I CMPSS-3 Low Comparator Negative Input 1 K3 29 21
CMP3_LP2 I CMPSS-3 Low Comparator Positive Input 2 N3 41 33 22
CMP3_LP3 I CMPSS-3 Low Comparator Positive Input 3 245 T13 76
CMP3_LP4 I CMPSS-3 Low Comparator Positive Input 4 T5 59 51
CMP4_HN0 I CMPSS-4 High Comparator Negative Input 0 P1 43 35 24
CMP4_HN1 I CMPSS-4 High Comparator Negative Input 1 241 N11 66 55
CMP4_HP1 I CMPSS-4 High Comparator Positive Input 1 241 N11 66 55
CMP4_HP3 I CMPSS-4 High Comparator Positive Input 3 R5 57 49 34
CMP4_HP4 I CMPSS-4 High Comparator Positive Input 4 T6 60 52
CMP4_LN0 I CMPSS-4 Low Comparator Negative Input 0 P1 43 35 24
CMP4_LN1 I CMPSS-4 Low Comparator Negative Input 1 241 N11 66 55
CMP4_LP1 I CMPSS-4 Low Comparator Positive Input 1 241 N11 66 55
CMP4_LP3 I CMPSS-4 Low Comparator Positive Input 3 R5 57 49 34
CMP4_LP4 I CMPSS-4 Low Comparator Positive Input 4 T6 60 52
CMP5_HN0 I CMPSS-5 High Comparator Negative Input 0 M6
CMP5_HN1 I CMPSS-5 High Comparator Negative Input 1 248 P13 73 62
CMP5_HP0 I CMPSS-5 High Comparator Positive Input 0 M7
CMP5_HP1 I CMPSS-5 High Comparator Positive Input 1 248 P13 73 62
CMP5_HP2 I CMPSS-5 High Comparator Positive Input 2 249 N13 74 63
CMP5_HP5 I CMPSS-5 High Comparator Positive Input 5 237 M9 64
CMP5_LN0 I CMPSS-5 Low Comparator Negative Input 0 M6
CMP5_LN1 I CMPSS-5 Low Comparator Negative Input 1 248 P13 73 62
CMP5_LP0 I CMPSS-5 Low Comparator Positive Input 0 M7
CMP5_LP1 I CMPSS-5 Low Comparator Positive Input 1 248 P13 73 62
CMP5_LP2 I CMPSS-5 Low Comparator Positive Input 2 249 N13 74 63
CMP5_LP3 I CMPSS-5 Low Comparator Positive Input 3 240 N10 65
CMP5_LP4 I CMPSS-5 Low Comparator Positive Input 4 234 G2 16 13
CMP5_LP5 I CMPSS-5 Low Comparator Positive Input 5 T8
CMP6_HN0 I CMPSS-6 High Comparator Negative Input 0 245 T13 76
CMP6_HN1 I CMPSS-6 High Comparator Negative Input 1 T11
CMP6_HP0 I CMPSS-6 High Comparator Positive Input 0 244 R13 75
CMP6_HP1 I CMPSS-6 High Comparator Positive Input 1 T11
CMP6_HP2 I CMPSS-6 High Comparator Positive Input 2 P10
CMP6_HP4 I CMPSS-6 High Comparator Positive Input 4 227 H3 21
CMP6_LN0 I CMPSS-6 Low Comparator Negative Input 0 245 T13 76
CMP6_LN1 I CMPSS-6 Low Comparator Negative Input 1 T11
CMP6_LP0 I CMPSS-6 Low Comparator Positive Input 0 244 R13 75
CMP6_LP1 I CMPSS-6 Low Comparator Positive Input 1 T11
CMP6_LP2 I CMPSS-6 Low Comparator Positive Input 2 P10
CMP6_LP4 I CMPSS-6 Low Comparator Positive Input 4 235 G1 15 12
CMP6_LP5 I CMPSS-6 Low Comparator Positive Input 5 N7
CMP7_HN0 I CMPSS-7 High Comparator Negative Input 0 R5 57 49 34
CMP7_HN1 I CMPSS-7 High Comparator Negative Input 1 K4 30 22
CMP7_HP1 I CMPSS-7 High Comparator Positive Input 1 K4 30 22
CMP7_HP2 I CMPSS-7 High Comparator Positive Input 2 K3 29 21
CMP7_HP4 I CMPSS-7 High Comparator Positive Input 4 228 G3 18
CMP7_LN0 I CMPSS-7 Low Comparator Negative Input 0 R5 57 49 34
CMP7_LN1 I CMPSS-7 Low Comparator Negative Input 1 K4 30 22
CMP7_LP1 I CMPSS-7 Low Comparator Positive Input 1 K4 30 22
CMP7_LP2 I CMPSS-7 Low Comparator Positive Input 2 K3 29 21
CMP7_LP4 I CMPSS-7 Low Comparator Positive Input 4 J2
CMP7_LP5 I CMPSS-7 Low Comparator Positive Input 5 P7
CMP8_HN0 I CMPSS-8 High Comparator Negative Input 0 240 N10 65
CMP8_HN1 I CMPSS-8 High Comparator Negative Input 1 246 P11 67 56 38
CMP8_HP1 I CMPSS-8 High Comparator Positive Input 1 246 P11 67 56 38
CMP8_HP2 I CMPSS-8 High Comparator Positive Input 2 247 R11 68 57 39
CMP8_HP4 I CMPSS-8 High Comparator Positive Input 4 229 G4 17
CMP8_HP5 I CMPSS-8 High Comparator Positive Input 5 N8
CMP8_LN0 I CMPSS-8 Low Comparator Negative Input 0 240 N10 65
CMP8_LN1 I CMPSS-8 Low Comparator Negative Input 1 246 P11 67 56 38
CMP8_LP1 I CMPSS-8 Low Comparator Positive Input 1 246 P11 67 56 38
CMP8_LP2 I CMPSS-8 Low Comparator Positive Input 2 247 R11 68 57 39
CMP8_LP3 I CMPSS-8 Low Comparator Positive Input 3 226 H4 22 16
CMP8_LP4 I CMPSS-8 Low Comparator Positive Input 4 J1
CMP8_LP5 I CMPSS-8 Low Comparator Positive Input 5 N6
CMP9_HN0 I CMPSS-9 High Comparator Negative Input 0 M1 36 28
CMP9_HN1 I CMPSS-9 High Comparator Negative Input 1 T9
CMP9_HP1 I CMPSS-9 High Comparator Positive Input 1 N4 51 43
CMP9_HP2 I CMPSS-9 High Comparator Positive Input 2 225 K5 25 17 12
CMP9_HP4 I CMPSS-9 High Comparator Positive Input 4 230 J5 24
CMP9_HP5 I CMPSS-9 High Comparator Positive Input 5 J4
CMP9_LN0 I CMPSS-9 Low Comparator Negative Input 0 M1 36 28
CMP9_LN1 I CMPSS-9 Low Comparator Negative Input 1 T9
CMP9_LP1 I CMPSS-9 Low Comparator Positive Input 1 N4 51 43
CMP9_LP2 I CMPSS-9 Low Comparator Positive Input 2 225 K5 25 17 12
CMP9_LP3 I CMPSS-9 Low Comparator Positive Input 3 239 P12 70 59 41
CMP9_LP4 I CMPSS-9 Low Comparator Positive Input 4 M5 52 44
CMP9_LP5 I CMPSS-9 Low Comparator Positive Input 5 P6
CMP10_HN0 I CMPSS-10 High Comparator Negative Input 0 T10
CMP10_HN1 I CMPSS-10 High Comparator Negative Input 1 M7
CMP10_HP1 I CMPSS-10 High Comparator Positive Input 1 R10
CMP10_HP2 I CMPSS-10 High Comparator Positive Input 2 P9
CMP10_HP4 I CMPSS-10 High Comparator Positive Input 4 231 H5 23
CMP10_HP5 I CMPSS-10 High Comparator Positive Input 5 J3
CMP10_LN0 I CMPSS-10 Low Comparator Negative Input 0 T10
CMP10_LN1 I CMPSS-10 Low Comparator Negative Input 1 M7
CMP10_LP1 I CMPSS-10 Low Comparator Positive Input 1 R10
CMP10_LP2 I CMPSS-10 Low Comparator Positive Input 2 P9
CMP10_LP4 I CMPSS-10 Low Comparator Positive Input 4 P5 55 47
CMP10_LP5 I CMPSS-10 Low Comparator Positive Input 5 R7
CMP11_HN0 I CMPSS-11 High Comparator Negative Input 0 230 J5 24
CMP11_HN1 I CMPSS-11 High Comparator Negative Input 1 N4 51 43
CMP11_HP1 I CMPSS-11 High Comparator Positive Input 1 R9
CMP11_HP2 I CMPSS-11 High Comparator Positive Input 2 N9
CMP11_HP5 I CMPSS-11 High Comparator Positive Input 5 P8
CMP11_LN0 I CMPSS-11 Low Comparator Negative Input 0 230 J5 24
CMP11_LN1 I CMPSS-11 Low Comparator Negative Input 1 N4 51 43
CMP11_LP1 I CMPSS-11 Low Comparator Positive Input 1 R9
CMP11_LP2 I CMPSS-11 Low Comparator Positive Input 2 N9
CMP11_LP4 I CMPSS-11 Low Comparator Positive Input 4 N5 56 48
CMP11_LP5 I CMPSS-11 Low Comparator Positive Input 5 T7
CMP12_HN0 I CMPSS-12 High Comparator Negative Input 0 224 L5 26 18 13
CMP12_HP5 I CMPSS-12 High Comparator Positive Input 5 R8
CMP12_LN0 I CMPSS-12 Low Comparator Negative Input 0 224 L5 26 18 13
CMP12_LP0 I CMPSS-12 Low Comparator Positive Input 0 238 N12 69 58 40
CMP12_LP4 I CMPSS-12 Low Comparator Positive Input 4 236 M8 63
D0 I ADC-D Input 0 R3 47 39 28
D1 I ADC-D Input 1 T3 48 40 29
D2 I ADC-D Input 2 R5 57 49 34
D3 I ADC-D Input 3 R6 58 50 35
D4 I ADC-D Input 4 240 N10 65
D5 I ADC-D Input 5 241 N11 66 55
D6 I ADC-D Input 6 242 T12 71 60
D7 I ADC-D Input 7 243 R12 72 61
D8 I ADC-D Input 8 244 R13 75
D9 I ADC-D Input 9 245 T13 76
D10 I ADC-D Input 10 N6
D11 I ADC-D Input 11 P6
D12 I ADC-D Input 12 M7
D13 I ADC-D Input 13 M6
D14 I ADC-D Input 14 M3 40 32 21
D15 I ADC-D Input 15 M4 39 31 20
D16 I ADC-D Input 16 R7
D17 I ADC-D Input 17 T7
D24 I ADC-D Input 24 M1 36 28
D25 I ADC-D Input 25 M2 35 27
D26 I ADC-D Input 26 L4 34 26 17
D27 I ADC-D Input 27 L3 33 25 16
D28 I ADC-D Input 28 L2 32 24
D29 I ADC-D Input 29 L1 31 23
D30 I ADC-D Input 30 K4 30 22
D31 I ADC-D Input 31 K3 29 21
DACA_OUT O Buffered DAC-A Output. R1 44 36 25
DACB_OUT O Buffered DAC-B Output. P3 49 41 30
E0 I ADC-E Input 0 P3 49 41 30
E1 I ADC-E Input 1 P4 50 42 31
E2 I ADC-E Input 2 T5 59 51
E3 I ADC-E Input 3 T6 60 52
E4 I ADC-E Input 4 246 P11 67 56 38
E5 I ADC-E Input 5 247 R11 68 57 39
E6 I ADC-E Input 6 248 P13 73 62
E7 I ADC-E Input 7 249 N13 74 63
E8 I ADC-E Input 8 T10
E9 I ADC-E Input 9 T9
E10 I ADC-E Input 10 R10
E11 I ADC-E Input 11 R9
E12 I ADC-E Input 12 P9
E13 I ADC-E Input 13 N9
E14 I ADC-E Input 14 M3 40 32 21
E15 I ADC-E Input 15 M4 39 31 20
E16 I ADC-E Input 16 P10
E17 I ADC-E Input 17 T11
E24 I ADC-E Input 24 224 L5 26 18 13
E25 I ADC-E Input 25 225 K5 25 17 12
E26 I ADC-E Input 26 230 J5 24
E27 I ADC-E Input 27 231 H5 23
E28 I ADC-E Input 28 R2 45 37 26
E29 I ADC-E Input 29 T2 46 38 27
E30 I ADC-E Input 30 N4 51 43
E31 I ADC-E Input 31 M5 52 44
VDAC I Optional external reference voltage for on-chip DACs. P2 42 34 23
VREFHIAB I ADC-AB high reference. This voltage must be driven into the pin from external circuitry. Place at least a 2.2-µF capacitor on this pin for the 12-bit mode, or at least a 22-µF capacitor for the 16-bit mode. This capacitor should be placed as close to the device as possible between the VREFHI and VREFLO pins. NOTE: Do not load this pin externally N2 38 30 19
VREFHICDE I ADC-CDE high reference. This voltage must be driven into the pin from external circuitry. Place at least a 2.2-µF capacitor on this pin for the 12-bit mode, or at least a 22-µF capacitor for the 16-bit mode. This capacitor should be placed as close to the device as possible between the VREFHI and VREFLO pins. NOTE: Do not load this pin externally R4 54 46 33
VREFLOAB I ADC-AB Low Reference N1 37 29 18
VREFLOCDE I ADC-CDE Low Reference T4 53 45 32