SNOSCZ4A April   2015  – October 2024 FDC1004-Q1

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 I2C Interface Voltage Level
    7. 5.7 I2C Interface Timing
    8. 5.8 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 The Shield
      2. 6.3.2 The CAPDAC
      3. 6.3.3 Capacitive System Offset Calibration
      4. 6.3.4 Capacitive Gain Calibration
    4. 6.4 Device Functional Modes
      1. 6.4.1 Single Ended Measurement
      2. 6.4.2 Differential Measurement
    5. 6.5 Programming
      1. 6.5.1 Serial Bus Address
      2. 6.5.2 Read/Write Operations
      3. 6.5.3 Device Usage
        1. 6.5.3.1 Measurement Configuration
        2. 6.5.3.2 Triggering Measurements
        3. 6.5.3.3 Wait for Measurement Completion
        4. 6.5.3.4 Read of Measurement Result
    6. 6.6 Register Maps
      1. 6.6.1 Registers
        1. 6.6.1.1 Capacitive Measurement Registers
      2. 6.6.2 Measurement Registers
      3. 6.6.3 Measurement Configuration Registers
      4. 6.6.4 FDC Configuration Register
      5. 6.6.5 Offset Calibration Registers
      6. 6.6.6 Gain Calibration Registers
      7. 6.6.7 Manufacturer ID Register
      8. 6.6.8 Device ID Register
  8. 7 Applications and Implementation
    1. 7.1 Application Information
      1. 7.1.1 Liquid Level Sensor
    2. 7.2 Typical Application
      1. 7.2.1 Design Requirements
      2. 7.2.2 Detailed Design Procedure
      3. 7.2.3 Application Curve
    3. 7.3 Best Design Practices
    4. 7.4 Initialization Set Up
    5. 7.5 Power Supply Recommendations
    6. 7.6 Layout
      1. 7.6.1 Layout Guidelines
      2. 7.6.2 Layout Example
  9. 8 Device and Documentation Support
    1. 8.1 Documentation Support
      1. 8.1.1 Related Documentation
    2. 8.2 Receiving Notification of Documentation Updates
    3. 8.3 Support Resources
    4. 8.4 Trademarks
    5. 8.5 Electrostatic Discharge Caution
    6. 8.6 Glossary
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6.3.1 The Shield

The FDC1004-Q1 measures capacitance between CINn and ground. That means any capacitance to ground on signal path between the FDC1004-Q1 CINn pins and sensor is included in the FDC1004-Q1 conversion result.

In some applications, the parasitic capacitance of the sensor connections can be larger than the capacitance of the sensor. If that parasitic capacitance is stable, the capacitance can be treated as a constant capacitive offset. However, the parasitic capacitance of the sensor connections can have significant variation due to environmental changes (such as mechanical movement, temperature shifts, humidity changes). These changes are seen as drift in the conversion result and can significantly compromise the system accuracy.

To eliminate the CINn parasitic capacitance to ground, the FDC1004-Q1 SHLDx signals can be used for shielding the connection between the sensor and CINn. The SHLDx output is the same signal waveform as the excitation of the CINn pin; the SHLDx is driven to the same voltage potential as the CINn pin. Therefore, there is no current between CINn and SHLDx pins, and any capacitance between these pins does not affect the CINn charge transfer. Ideally, the CINn to SHLD capacitance does not have any contribution to the FDC1004-Q1 result.

In differential measurements, SHLD1 is assigned to CHn and SHLD2 is assigned to CHm, where n < m. For instance in the measurement CIN1 – CIN2, where CHA = CIN1 and CHB = CIN2 (see Table 6-4), SHDL1 is assigned to CIN1 and SHDL2 is assigned to CIN2.

In a single ended configuration, such as CINn vs. GND, SHLD1 is internally shorted to SHLD2. In a single ended configuration, such as CINn versus GND with CAPDAC enabled, SHLD1 is assigned to the selected channel, SHLD2 is floating.

For best results, locate the FDC1004-Q1 as close as possible to the capacitive sensor. Minimize the connection length between the sensor and FDC1004-Q1 CINn pins and between the sensor ground and the FDC1004-Q1 GND pin. Shield the PCB traces to the CINn pins and connect the shielding to the FDC1004-Q1 SHLDx pins. In addition, if a shielded cable is used to connect the FDC1004-Q1 to the sensor, connect the shield to the appropriate SHLDx pin. In applications where only one SHLDx pin is used, the unused SHLDx pin can be left unconnected.

For more information on how to design a sensor with a shield, refer to the Capacitive Sensing: Ins and Outs of Active Sensing application note.