SNOSCZ5B June   2015  – October 2024 FDC2112 , FDC2114 , FDC2212 , FDC2214

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Comparison
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Switching Characteristics - I2C
    8. 6.8 Typical Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagrams
    3. 7.3 Feature Description
      1. 7.3.1 Clocking Architecture
      2. 7.3.2 Multi-Channel and Single-Channel Operation
      3. 7.3.3 Gain and Offset (FDC2112, FDC2114 Only)
      4. 7.3.4 Current Drive Control Registers
      5. 7.3.5 Device Status Registers
      6. 7.3.6 Input Deglitch Filter
    4. 7.4 Device Functional Modes
      1. 7.4.1 Start-Up Mode
      2. 7.4.2 Normal (Conversion) Mode
      3. 7.4.3 Sleep Mode
      4. 7.4.4 Shutdown Mode
        1. 7.4.4.1 Reset
    5. 7.5 Programming
      1. 7.5.1 I2C Interface Specifications
    6. 7.6 Register Maps
      1. 7.6.1  Register List
      2. 7.6.2  Address 0x00, DATA_CH0
      3. 7.6.3  Address 0x01, DATA_LSB_CH0 (FDC2212 / FDC2214 only)
      4. 7.6.4  Address 0x02, DATA_CH1
      5. 7.6.5  Address 0x03, DATA_LSB_CH1 (FDC2212 / FDC2214 only)
      6. 7.6.6  Address 0x04, DATA_CH2 (FDC2114, FDC2214 only)
      7. 7.6.7  Address 0x05, DATA_LSB_CH2 (FDC2214 only)
      8. 7.6.8  Address 0x06, DATA_CH3 (FDC2114, FDC2214 only)
      9. 7.6.9  Address 0x07, DATA_LSB_CH3 (FDC2214 only)
      10. 7.6.10 Address 0x08, RCOUNT_CH0
      11. 7.6.11 Address 0x09, RCOUNT_CH1
      12. 7.6.12 Address 0x0A, RCOUNT_CH2 (FDC2114, FDC2214 only)
      13. 7.6.13 Address 0x0B, RCOUNT_CH3 (FDC2114, FDC2214 only)
      14. 7.6.14 Address 0x0C, OFFSET_CH0 (FDC21112 / FDC2114 only)
      15. 7.6.15 Address 0x0D, OFFSET_CH1 (FDC21112 / FDC2114 only)
      16. 7.6.16 Address 0x0E, OFFSET_CH2 (FDC2114 only)
      17. 7.6.17 Address 0x0F, OFFSET_CH3 (FDC2114 only)
      18. 7.6.18 Address 0x10, SETTLECOUNT_CH0
      19. 7.6.19 Address 0x11, SETTLECOUNT_CH1
      20. 7.6.20 Address 0x12, SETTLECOUNT_CH2 (FDC2114, FDC2214 only)
      21. 7.6.21 Address 0x13, SETTLECOUNT_CH3 (FDC2114, FDC2214 only)
      22. 7.6.22 Address 0x14, CLOCK_DIVIDERS_CH0
      23. 7.6.23 Address 0x15, CLOCK_DIVIDERS_CH1
      24. 7.6.24 Address 0x16, CLOCK_DIVIDERS_CH2 (FDC2114, FDC2214 only)
      25. 7.6.25 Address 0x17, CLOCK_DIVIDERS_CH3 (FDC2114, FDC2214 only)
      26. 7.6.26 Address 0x18, STATUS
      27. 7.6.27 Address 0x19, ERROR_CONFIG
      28. 7.6.28 Address 0x1A, CONFIG
      29. 7.6.29 Address 0x1B, MUX_CONFIG
      30. 7.6.30 Address 0x1C, RESET_DEV
      31. 7.6.31 Address 0x1E, DRIVE_CURRENT_CH0
      32. 7.6.32 Address 0x1F, DRIVE_CURRENT_CH1
      33. 7.6.33 Address 0x20, DRIVE_CURRENT_CH2 (FDC2114 / FDC2214 only)
      34. 7.6.34 Address 0x21, DRIVE_CURRENT_CH3 (FDC2114 / FDC2214 only)
      35. 7.6.35 Address 0x7E, MANUFACTURER_ID
      36. 7.6.36 Address 0x7F, DEVICE_ID
  9. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Sensor Configuration
      2. 8.1.2 Shield
      3. 8.1.3 Power-Cycled Applications
      4. 8.1.4 Inductor Self-Resonant Frequency
      5. 8.1.5 Application Curves
    2. 8.2 Typical Application
      1. 8.2.1 Schematic
      2. 8.2.2 Design Requirements
      3. 8.2.3 Detailed Design Procedure
        1. 8.2.3.1 Recommended Initial Register Configuration Values
      4. 8.2.4 Application Curve
    3. 8.3 Best Design Practices
    4. 8.4 Power Supply Recommendations
    5. 8.5 Layout
      1. 8.5.1 Layout Guidelines
      2. 8.5.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Receiving Notification of Documentation Updates
    2. 9.2 Support Resources
    3. 9.3 Trademarks
    4. 9.4 Electrostatic Discharge Caution
    5. 9.5 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7.3.3 Gain and Offset (FDC2112, FDC2114 Only)

The FDC2112 and FDC2114 have internal 16-bit data converters, but the standard conversion output word width is only 12 bits; therefore only 12 of the 16 bits are available from the data registers. By default, the gain feature is disabled and the DATA registers contain the 12 MSBs of the 16-bit word. However, it is possible to shift the data output by up to 4 bits. Figure 7-6 illustrates the segment of the 16-bit sample that is reported for each possible gain setting.

FDC2212 FDC2214 FDC2112 FDC2114 Conversion Data Output GainFigure 7-6 Conversion Data Output Gain

For systems in which the sensor signal variation is less than 25% of the full-scale range, the FDC can report conversion results with higher resolution by setting the Output Gain. The Output Gain is applied to all device channels. An output gain can be used to apply a 2-bit, 3-bit, or 4-bit shift to the output code for all channels, allowing access to the 4 LSBs of the original 16-bit result. The MSBs of the sample are shifted out when a gain is applied. Do not use the output gain if the MSBs of any active channel are toggling, as the MSBs for that channel are lost when gain is applied.

Example: If the conversion result for a channel is 0x07A3, with OUTPUT_GAIN=0x0, the reported output code is 0x07A. If OUTPUT_GAIN is set to 0x3 in the same condition, then the reported output code is 0x7A3. The original 4 MSBs (0x0) are no longer accessible.

Table 7-7 Output Gain Register (FDC2112 and FDC2114 Only)
CHANNEL(1)REGISTERFIELD [ BIT(S) ]VALUESEFFECTIVE RESOLUTION (BITS)OUTPUT RANGE
AllRESET_DEV, addr 0x1COUTPUT_GAIN [ 10:9 ]00 (default): Gain =1 (0 bits shift)12100% full scale
01: Gain = 4 (2 bits left shift)1425% full scale
10: Gain = 8 (3 bits left shift)1512.5% full scale
11 : Gain = 16 (4 bits left shift)166.25% full scale
(1) Channels 2 and 3 are available for FDC2114 only.

An offset value can be subtracted from each DATA value to compensate for a frequency offset or maximize the dynamic range of the sample data. Make sure the offset values < fSENSORx_MIN / fREFx. Otherwise, the offset might be so large that the offset masks the LSBs which are changing.

Table 7-8 Frequency Offset Registers
CHANNEL(1)REGISTERFIELD [ BIT(S) ]VALUE
0OFFSET_CH0, addr 0x0CCH0_OFFSET [ 15:0 ]fOFFSET0 = CH0_OFFSET * (fREF0/216)
1OFFSET_CH1, addr 0x0DCH1_OFFSET [ 15:0 ]fOFFSET1 = CH1_OFFSET * (fREF1/216)
2OFFSET_CH2, addr 0x0ECH2_OFFSET [ 15:0 ]fOFFSET2 = CH2_OFFSET * (fREF2/216)
3OFFSET_CH3, addr 0x0FCH3_OFFSET [ 15:0 ]fOFFSET3 = CH3_OFFSET * (fREF3/216)
(1) Channels 2 and 3 are only available for FDC2114 and FDC2214.

The sensor capacitance CSENSE of a differential sensor configuration can be determined by:

Equation 7. FDC2212 FDC2214 FDC2112 FDC2114

where

The FDC2112 and FDC2114 sensor frequency fSENSORx can be determined by:

Equation 8. FDC2212 FDC2214 FDC2112 FDC2114

where

  • DATAx = Conversion result from the DATA_CHx register
  • CHx_OFFSET = Offset value set in the OFFSET_CHx register
  • OUTPUT_GAIN = output multiplication factor set in the RESET_DEVICE.OUTPUT_GAIN register

The FDC2212 and FDC2214 sensor frequency fSENSORx can be determined by:

Equation 9. FDC2212 FDC2214 FDC2112 FDC2114 (FDC2212, FDC2214)

where

  • DATAx = Conversion result from the DATA_CHx register