SNOSCZ5B June   2015  – October 2024 FDC2112 , FDC2114 , FDC2212 , FDC2214

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Comparison
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Switching Characteristics - I2C
    8. 6.8 Typical Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagrams
    3. 7.3 Feature Description
      1. 7.3.1 Clocking Architecture
      2. 7.3.2 Multi-Channel and Single-Channel Operation
      3. 7.3.3 Gain and Offset (FDC2112, FDC2114 Only)
      4. 7.3.4 Current Drive Control Registers
      5. 7.3.5 Device Status Registers
      6. 7.3.6 Input Deglitch Filter
    4. 7.4 Device Functional Modes
      1. 7.4.1 Start-Up Mode
      2. 7.4.2 Normal (Conversion) Mode
      3. 7.4.3 Sleep Mode
      4. 7.4.4 Shutdown Mode
        1. 7.4.4.1 Reset
    5. 7.5 Programming
      1. 7.5.1 I2C Interface Specifications
    6. 7.6 Register Maps
      1. 7.6.1  Register List
      2. 7.6.2  Address 0x00, DATA_CH0
      3. 7.6.3  Address 0x01, DATA_LSB_CH0 (FDC2212 / FDC2214 only)
      4. 7.6.4  Address 0x02, DATA_CH1
      5. 7.6.5  Address 0x03, DATA_LSB_CH1 (FDC2212 / FDC2214 only)
      6. 7.6.6  Address 0x04, DATA_CH2 (FDC2114, FDC2214 only)
      7. 7.6.7  Address 0x05, DATA_LSB_CH2 (FDC2214 only)
      8. 7.6.8  Address 0x06, DATA_CH3 (FDC2114, FDC2214 only)
      9. 7.6.9  Address 0x07, DATA_LSB_CH3 (FDC2214 only)
      10. 7.6.10 Address 0x08, RCOUNT_CH0
      11. 7.6.11 Address 0x09, RCOUNT_CH1
      12. 7.6.12 Address 0x0A, RCOUNT_CH2 (FDC2114, FDC2214 only)
      13. 7.6.13 Address 0x0B, RCOUNT_CH3 (FDC2114, FDC2214 only)
      14. 7.6.14 Address 0x0C, OFFSET_CH0 (FDC21112 / FDC2114 only)
      15. 7.6.15 Address 0x0D, OFFSET_CH1 (FDC21112 / FDC2114 only)
      16. 7.6.16 Address 0x0E, OFFSET_CH2 (FDC2114 only)
      17. 7.6.17 Address 0x0F, OFFSET_CH3 (FDC2114 only)
      18. 7.6.18 Address 0x10, SETTLECOUNT_CH0
      19. 7.6.19 Address 0x11, SETTLECOUNT_CH1
      20. 7.6.20 Address 0x12, SETTLECOUNT_CH2 (FDC2114, FDC2214 only)
      21. 7.6.21 Address 0x13, SETTLECOUNT_CH3 (FDC2114, FDC2214 only)
      22. 7.6.22 Address 0x14, CLOCK_DIVIDERS_CH0
      23. 7.6.23 Address 0x15, CLOCK_DIVIDERS_CH1
      24. 7.6.24 Address 0x16, CLOCK_DIVIDERS_CH2 (FDC2114, FDC2214 only)
      25. 7.6.25 Address 0x17, CLOCK_DIVIDERS_CH3 (FDC2114, FDC2214 only)
      26. 7.6.26 Address 0x18, STATUS
      27. 7.6.27 Address 0x19, ERROR_CONFIG
      28. 7.6.28 Address 0x1A, CONFIG
      29. 7.6.29 Address 0x1B, MUX_CONFIG
      30. 7.6.30 Address 0x1C, RESET_DEV
      31. 7.6.31 Address 0x1E, DRIVE_CURRENT_CH0
      32. 7.6.32 Address 0x1F, DRIVE_CURRENT_CH1
      33. 7.6.33 Address 0x20, DRIVE_CURRENT_CH2 (FDC2114 / FDC2214 only)
      34. 7.6.34 Address 0x21, DRIVE_CURRENT_CH3 (FDC2114 / FDC2214 only)
      35. 7.6.35 Address 0x7E, MANUFACTURER_ID
      36. 7.6.36 Address 0x7F, DEVICE_ID
  9. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Sensor Configuration
      2. 8.1.2 Shield
      3. 8.1.3 Power-Cycled Applications
      4. 8.1.4 Inductor Self-Resonant Frequency
      5. 8.1.5 Application Curves
    2. 8.2 Typical Application
      1. 8.2.1 Schematic
      2. 8.2.2 Design Requirements
      3. 8.2.3 Detailed Design Procedure
        1. 8.2.3.1 Recommended Initial Register Configuration Values
      4. 8.2.4 Application Curve
    3. 8.3 Best Design Practices
    4. 8.4 Power Supply Recommendations
    5. 8.5 Layout
      1. 8.5.1 Layout Guidelines
      2. 8.5.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Receiving Notification of Documentation Updates
    2. 9.2 Support Resources
    3. 9.3 Trademarks
    4. 9.4 Electrostatic Discharge Caution
    5. 9.5 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7.3.2 Multi-Channel and Single-Channel Operation

The multi-channel package of the FDC enables the user to save board space and support flexible system design. For example, temperature drift can often cause a shift in component values, resulting in a shift in resonant frequency of the sensor. Using a second sensor as a reference provides the capability to cancel out a temperature shift. When operated in multi-channel mode, the FDC sequentially samples the active channels. In single-channel mode, the FDC samples a single channel, which is selectable. Table 7-3 shows the registers and values that are used to configure either multi-channel or single-channel modes.

Table 7-3 Single- and Multi-Channel Configuration Registers
MODEREGISTERFIELD [ BIT(S) ]VALUE
Single channelCONFIG, addr 0x1AACTIVE_CHAN [15:14]00 = chan 0
01 = chan 1
10 = chan 2
11 = chan 3
MUX_CONFIG addr 0x1BAUTOSCAN_EN [15]0 = continuous conversion on a single channel (default)
Multi-channelMUX_CONFIG addr 0x1BAUTOSCAN_EN [15]1 = continuous conversion on multiple channels
MUX_CONFIG addr 0x1BRR_SEQUENCE [14:13]00 = Ch0, Ch 1
01 = Ch0, Ch 1, Ch 2
10 = Ch0, CH1, Ch2, Ch3

The digitized sensor measurement for each channel (DATAx) represents the ratio of the sensor frequency to the reference frequency.

The data output (DATAx) of the FDC2112 and FDC2114 is expressed as the 12 MSBs of a 16-bit result:

Equation 1. FDC2212 FDC2214 FDC2112 FDC2114

The data output (DATAx) of the FDC2212 and FDC2214 is expressed as:

Equation 2. FDC2212 FDC2214 FDC2112 FDC2114

Table 7-4 illustrates the registers that contain the fixed point sample values for each channel.

Table 7-4 Sample Data Registers
CHANNEL(2)REGISTER(1)FIELD NAME [ BITS(S) ] AND VALUE (FDC2112, FDC2114)FIELD NAME [ BITS(S) ] AND VALUE (FDC2212, FDC2214) (3)(4)
0DATA_CH0, addr 0x00DATA0 [11:0]:
12 bits of the 16 bit result.
0x000 = under range
0xfff = over range		DATA0 [27:16]:
12 MSBs of the 28 bit result
DATA_LSB_CH0, addr 0x01Not applicableDATA0 [15:0]:
16 LSBs of the 28 bit conversion result
1DATA_CH1, addr 0x02DATA1 [11:0]:
12 bits of the 16 bit result.
0x000 = under range
0xfff = over range		DATA1 [27:16]:
12 MSBs of the 28 bit result
DATA_LSB_CH1, addr 0x03Not applicableDATA1 [15:0]:
16 LSBs of the 28 bit conversion result
2DATA_CH2, addr 0x04DATA2 [11:0]:
12 bits of the 16 bit result.
0x000 = under range
0xfff = over range		DATA2 [27:16]:
12 MSBs of the 28 bit result
DATA_LSB_CH2, addr 0x05Not applicableDATA2 [15:0]:
16 LSBs of the 28 bit conversion result
3DATA_CH3, addr 0x06DATA3 [11:0]:
12 bits of the 16 bit result.
0x000 = under range
0xfff = over range		DATA3 [27:16]:
12 MSBs of the 28 bit result
DATA_LSB_CH3, addr 0x07Not applicableDATA3 [15:0]:
16 LSBs of the 28 bit conversion result
(1) The DATA_CHx.DATAx register must always be read first, followed by the DATA_LSB_ CHx.DATAx register of the same channel to ensure data coherency.
(2) Channels 2 and 3 are only available for FDC2114 and FDC2214.
(3) A DATA value of 0x0000000 = under range for FDC2212/FDC2214.
(4) A DATA value of 0xFFFFFFF = over range for FDC2212/FDC2214.

When the FDC sequences through the channels in multi-channel mode, the dwell time interval for each channel is the sum of three parts:

  1. sensor activation time
  2. conversion time
  3. channel switch delay

The sensor activation time is the amount of settling time required for the sensor oscillation to stabilize, as shown in Figure 7-4. The settling wait time is programmable, and TI recommends setting the wait time to a value that is long enough to allow stable oscillation. The settling wait time for channel x is given by:

Equation 3. tSx = (CHX_SETTLECOUNTˣ16)/fREFx

Table 7-5 illustrates the registers and values for configuring the settling time for each channel.

FDC2212 FDC2214 FDC2112 FDC2114 Multi-Channel Mode SequencingFigure 7-4 Multi-Channel Mode Sequencing
FDC2212 FDC2214 FDC2112 FDC2114 Single-Channel Mode SequencingFigure 7-5 Single-Channel Mode Sequencing
Table 7-5 Settling Time Register Configuration
CHANNEL(1)REGISTERFIELDCONVERSION TIME(2)
0SETTLECOUNT_CH0, addr 0x10CH0_SETTLECOUNT [15:0](CH0_SETTLECOUNT*16)/fREF0
1SETTLECOUNT_CH1, addr 0x11CH1_SETTLECOUNT [15:0](CH1_SETTLECOUNT*16)/fREF1
2SETTLECOUNT_CH2, addr 0x12CH2_SETTLECOUNT [15:0](CH2_SETTLECOUNT*16)/fREF2
3SETTLECOUNT_CH3, addr 0x13CH3_SETTLECOUNT [15:0](CH3_SETTLECOUNT*16)/fREF3
(1) Channels 2 and 3 are available only in the FDC2114 and FDC2214.
(2) fREFx is the reference frequency configured for the channel.

The SETTLECOUNT for any channel x must satisfy:

  • Equation 4. CHx_SETTLECOUNT > Vpk × fREFx × C × π2 / (32 × IDRIVEX)

    • where

    • Vpk = Peak oscillation amplitude at the programmed IDRIVE setting
    • fREFx = Reference frequency for Channel x
    • C = sensor capacitance including parasitic PCB capacitance
    • IDRIVEX = setting programmed into the IDRIVE register in amps

  • Round the result to the next highest integer (for example, if Equation 4 recommends a minimum value of 6.08, program the register to 7 or higher).

  • The conversion time represents the number of reference clock cycles used to measure the sensor frequency and is set by the CHx_RCOUNT register for the channel. The conversion time for any channel x is:

  • Equation 5. tCx = (CHx_RCOUNT ˣ 16 + 4) /fREFx

  • The reference count value must be chosen to support the required number of effective bits (ENOB). For example, if an ENOB of 13 bits is required, then a minimum conversion time of 213 = 8192 clock cycles is required. 8192 clock cycles correspond to a CHx_RCOUNT value of 0x0200.

Table 7-6 Conversion Time Configuration Registers, Channels 0 - 3(1)
CHANNELREGISTERFIELD [ BIT(S) ]CONVERSION TIME
0RCOUNT_CH0, addr 0x08CH0_RCOUNT [15:0](CH0_RCOUNT*16)/fREF0
1RCOUNT_CH1, addr 0x09CH1_RCOUNT [15:0](CH1_RCOUNT*16)/fREF1
2RCOUNT_CH2, addr 0x0ACH2_RCOUNT [15:0](CH2_RCOUNT*16)/fREF2
3RCOUNT_CH3, addr 0x0BCH3_RCOUNT [15:0](CH3_RCOUNT*16)/fREF3
(1) Channels 2 and 3 are available only for FDC2114 and FDC2214.

The typical channel switch delay time between the end of conversion and the beginning of sensor activation of the subsequent channel is:

Equation 6. Channel Switch Delay = 692ns + 5 / fref

The deterministic conversion time of the FDC allows data polling at a fixed interval. For example, if the programmed RCOUNT setting is 512 FREF cycles and SETTLECOUNT is 128 FREF cycles, then one conversion takes 1.8ms (sensor-activation time) + 3.2ms (conversion time) + 0.75ms (channel-switch delay) = 16.75ms per channel. If the FDC is configured for dual-channel operation by setting AUTOSCAN_EN = 1 and RR_SEQUENCE = 00, then one full set of conversion results are available from the data registers every 33.5ms.

A data ready flag (DRDY) is also available for interrupt driven system designs (see the STATUS register description in Register Maps).