SLLS206L May   2005  – August 2024 GD65232 , GD75232

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  Recommended Operating Conditions
    3. 5.3  Thermal Information
    4. 5.4  Supply Currents over Recommended Operating Free-air Temperature Range
    5. 5.5  Electrical Characteristics, Driver
    6. 5.6  Switching Characteristics, Driver
    7. 5.7  Electrical Characteristics, Receiver
    8. 5.8  Switching Characteristics, Receiver
    9. 5.9  Typical Characteristics Driver
    10. 5.10 Typical Characteristics Receiver
  7. 6 Parameter Measurement Information
  8. 7 Application and Implementation
    1. 7.1 Application Information
    2. 7.2 Schematic
  9. 8 Device and Documentation Support
    1. 8.1 Receiving Notification of Documentation Updates
    2. 8.2 Support Resources
    3. 8.3 Trademarks
    4. 8.4 Electrostatic Discharge Caution
    5. 8.5 Glossary
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

3 Description

The GD65232 and GD75232 combine three drivers and five receivers from the Texas Instruments trade-standard SN75188 and SN75189 bipolar quadruple drivers and receivers, respectively. The pinout matches the flow-through design of the SN75C185 to decrease the part count, reduce the board space required, and allow easy interconnection of the UART and serial-port connector of an IBM™ PC/AT and compatibles. The bipolar circuits and processing of the GD65232 and GD75232 provide a rugged, low-cost solution for this function at the expense of quiescent power and external passive components relative to the SN75C185.

The GD65232 and GD75232 comply with the requirements of the TIA/EIA-232-F and ITU (formerly CCITT) V.28 standards. These standards are for data interchange between a host computer and a peripheral at signaling rates up to 20kbits. The switching speeds of these devices are fast enough to support rates up to 120kbits with lower capacitive loads (shorter cables). Interoperability at the higher signaling rates cannot be expected unless the designer has design control of the cable and the interface circuits at both ends. For interoperability at signaling rates up to 120kbits, use of TIA/EIA-423-B (ITU V.10) and TIA/EIA-422-B (ITU V.11) standards is recommended.

Package Information
PART NUMBER PACKAGE(1) PACKAGE SIZE(2)
GD65232
GD75232		 SSOP (DB, 20) 7.2mm x 7.8mm
SOIC (DW, 20) 12.8mm x 10.3mm
PDIP (N, 20) 24.33mm x 9.4mm
TSSOP (PW, 20) 6.5mm x 6.4mm
(1) For more information, see Section 10.
(2) The package size (length × width) is a nominal value and includes pins, where applicable.
GD65232 GD75232 Logic Diagram (positive logic) Logic Diagram (positive logic)