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  • HD3SS3212x Two-Channel Differential 2:1/1:2 USB3.1 Mux/Demux

    • SLASE74F May   2015  – September 2016 HD3SS3212

      PRODUCTION DATA.  

  • CONTENTS
  • SEARCH
  • HD3SS3212x Two-Channel Differential 2:1/1:2 USB3.1 Mux/Demux
  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 High-Speed Performance Parameters
    7. 7.7 Switching Characteristics
  8. 8 Parameter Measurement Information
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1 Output Enable and Power Savings
    4. 9.4 Device Functional Modes
  10. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Applications
      1. 10.2.1 Down Facing Port for USB3.1 Type C
        1. 10.2.1.1 Design Requirements
        2. 10.2.1.2 Detailed Design Procedure
        3. 10.2.1.3 Application Curves
    3. 10.3 Systems Examples
      1. 10.3.1 Up Facing Port for USB3.1 Type C
      2. 10.3.2 PCIE/SATA/USB
      3. 10.3.3 PCIE/eSATA
      4. 10.3.4 USB/eSATA
      5. 10.3.5 MIPI Camera Serial Interface
  11. 11Power Supply Recommendations
  12. 12Layout
    1. 12.1 Layout Guidelines
    2. 12.2 Layout Example
  13. 13Device and Documentation Support
    1. 13.1 Related Links
    2. 13.2 Receiving Notification of Documentation Updates
    3. 13.3 Community Resources
    4. 13.4 Trademarks
    5. 13.5 Electrostatic Discharge Caution
    6. 13.6 Glossary
  14. 14Mechanical, Packaging, and Orderable Information
  15. IMPORTANT NOTICE

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • RKS|20
Thermal pad, mechanical data (Package|Pins)
Orderable Information
  • slase74f_oa
  • slase74f_pm
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    • Full reading width
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    • Expanded reading width
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DATA SHEET

HD3SS3212x Two-Channel Differential 2:1/1:2 USB3.1 Mux/Demux

1 Features

  • Provides MUX/DEMUX Solution for USB Type-C™ Ecosystem for USB 3.1 Gen 1 and Gen 2 Data Rates
  • Compatible With MIPI DSI/CSI, FPDLinkIII, LVDS, and PCIE Gen II, III
  • Operates up to 10 Gbps
  • Wide –3-dB Differential BW of over 8 GHz
  • Excellent Dynamic Characteristics (at 5 GHz)
    • Crosstalk = –32 dB
    • Off Isolation = –19 dB
    • Insertion Loss = –1.6 dB
    • Return Loss = –12 dB
  • Bidirectional "Mux/De-Mux" Differential Switch
  • Supports Common Mode Voltage 0 to 2 V
  • Single Supply Voltage VCC of 3.3 V
  • Commercial Temperature Range of 0°C to 70°C (HD3SS3212RKS)
  • Industrial Temperature Range of –40°C to 85°C (HD3SS3212IRKS)

2 Applications

  • USB Type-C™ Ecosystem
  • Desktop and Notebook PCs
  • Server/Storage Area Networks
  • PCI Express Backplanes
  • Shared I/O Ports
  • FPDLinkII and FPDLinkIII Switching

3 Description

The HD3SS3212 is a high-speed bidirectional passive switch in mux or demux configurations suited for USB Type-C™ application supporting USB 3.1 Gen 1 and Gen 2 data rates. Based on control pin SEL, the device provides switching on differential channels between Port B or Port C to Port A.

The HD3SS3212 is a generic analog differential passive switch that can work for any high-speed interface applications requiring a common mode voltage range of 0 to 2 V and differential signaling with differential amplitude up to 1800 mVpp. It employs adaptive tracking that ensures the channel remains unchanged for the entire common mode voltage range.

Excellent dynamic characteristics of the device allow high-speed switching with minimum attenuation to the signal eye diagram with very little added jitter. It consumes <2 mW of power when operational and has a shutdown mode exercisable by OEn pin resulting <20 µW.

Device Information(1)

PART NUMBER PACKAGE BODY SIZE (NOM)
HD3SS3212 VQFN (20) 2.50 mm × 4.50 mm ×
0.5-mm pitch
HD3SS3212I
  1. For all available packages, see the orderable addendum at the end of the data sheet.

SPACE

Simplified Schematic

HD3SS3212 HD3SS3212I fbd_LASE74.gif

Pinout

HD3SS3212 HD3SS3212I po_LASE74.gif

4 Revision History

Changes from E Revision (May 2016) to F Revision

  • Deleted text "Internally tied to GND via 100-kΩ resistor." from the SEL pin in the Pin Functions tableGo

Changes from D Revision (March 2016) to E Revision

  • Changed Features From: Single Supply Voltage VCC of 3.3 V ±10% To: Single Supply Voltage VCC of 3.3 V Go
  • Changed text "HD3SS3212 requires 3.3-V ±10%" To: "HD3SS3212 requires 3.3-V" in the Design Requirements sectionGo
  • Changed Figure 11, moved 0.1 µF capacitors From: pins 7 and 8 To: pins 3 and 4Go

Changes from C Revision (January 2016) to D Revision

  • Changed the VCC MIN value From: 3 V To: 2.7 V in Recommended Operating Conditions Go

Changes from B Revision (January 2016) to C Revision

  • Changed the PINOUT image - pin 1 From: NC To: RSVD1 and pin 10 From: NC To: RSVD2 Go
  • Changed pin 1 From: NC To: RSVD1 , changed pin 10 From: NC To: RSVD2, and updated the Description in the Pin Functions tableGo

Changes from A Revision (August 2015) to B Revision

  • Changed the Vih MIN value From: 2 V To: 1.7 V in Recommended Operating Conditions Go

Changes from * Revision (May 2015) to A Revision

  • . Removed "or GND" from NC pin description Go
  • Updated Figure 16 Go

5 Device Comparison Table

OPERATING TEMPERATURE (°C) PACKAGE(1)(2) ORDERABLE PART NUMBER
0 to 70 RKS 20 pins HD3SS3212RKSR
–40 to 85 RKS 20 pins HD3SS3212IRKSR
(1) For the most current package and ordering information, see Mechanical, Packaging, and Orderable Information.
(2) Package drawings, thermal data, and symbolization are available at www.ti.com/packaging.

6 Pin Configuration and Functions

RKS Package
20-Pin VQFN
Top View
HD3SS3212 HD3SS3212I po_LASE74.gif

Pin Functions

PIN TYPE(1) DESCRIPTION
NAME NO.
VCC 6 P 3.3-V power
OEn 2 I Active-low chip enable
L: Normal operation
H: Shutdown
A0p 3 I/O Port A, channel 0, high-speed positive signal
A0n 4 I/O Port A, channel 0, high-speed negative signal
GND 5, 11, 20 G Ground
A1p 7 I/O Port A, channel 1, high-speed positive signal
A1n 8 I/O Port A, channel 1, high-speed negative signal
SEL 9 I Port select pin.
L: Port A to Port B
H: Port A to Port C
C1n 12 I/O Port C, channel 1, high-speed negative signal (connector side)
C1p 13 I/O Port C, channel 1, high-speed positive signal (connector side)
C0n 14 I/O Port C, channel 0, high-speed negative signal (connector side)
C0p 15 I/O Port C, channel 0, high-speed positive signal (connector side)
B1n 16 I/O Port B, channel 1, high-speed negative signal (connector side)
B1p 17 I/O Port B, channel 1, high-speed positive signal (connector side)
B0n 18 I/O Port B, channel 0, high-speed negative signal (connector side)
B0p 19 I/O Port B, channel 0, high-speed positive signal (connector side)
RSVD1 1 O Can be left not connected or can be fed to VCC
RSVD2 10 O
(1) The high-speed data ports incorporate 20-kΩ pulldown resistors that are switched in when a port is not selected and switched out when the port is selected.

7 Specifications

7.1 Absolute Maximum Ratings

see (1)
MIN MAX UNIT
VCC Supply voltage –0.5 4 V
Voltage Differential I/O –0.5 2.5 V
Control pins –0.5 VCC+ 0.5
Tstg Storage temperature –65 150 °C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

7.2 ESD Ratings

VALUE UNIT
V(ESD) Electrostatic discharge Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±2000 V
Charged-device model (CDM), per JEDEC specification JESD22-C101(2) ±500
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

7.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)
MIN MAX UNIT
VCC Supply voltage 2.7 3.6 V
Vih Input high voltage (SEL, OEn pins) 1.7 VCC V
Vil Input low voltage (SEL, OEn pins) –0.1 0.8 V
Vdiff High-speed signal pins differential voltage 0 1.8 Vpp
Vcm High speed signal pins common mode voltage 0 2 V
TA Operating free-air/ambient temperature HD3SS3212RKS 0 70 °C
HD3SS3212IRKS –40 85

7.4 Thermal Information

THERMAL METRIC(1) HD3SS3212 UNIT
RKS (VQFN)
20 PINS
RθJA Junction-to-ambient thermal resistance 46.6 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 41.8 °C/W
RθJB Junction-to-board thermal resistance 4.4 °C/W
ψJT Junction-to-top characterization parameter 17.6 °C/W
ψJB Junction-to-board characterization parameter 1.6 °C/W
RθJC(bot) Junction-to-case (bottom) thermal resistance 17.6 °C/W
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report.

7.5 Electrical Characteristics

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
ICC Device active current VCC = 3.3 V, OEn = 0 0.6 0.8 mA
ISTDN Device shutdown current VCC = 3.3 V, OEn = VCC 5 20 µA
CON Output ON capacitance 0.6 pF
COFF Output OFF capacitance 0.8 pF
RON Output ON resistance VCC = 3.3 V; VCM = 0 to 2 V;
IO = –8 mA		 5 8 Ω
ΔRON On-resistance match between pairs of the same channel VCC = 3.3 V; –0.35 V ≤ VIN ≤ 2.35 V; IO = –8 mA 0.5 Ω
RFLAT_ON On-resistance flatness RON(MAX) – RON(MAIN) VCC = 3.3 V; –0.35 V ≤ VIN ≤ 2.35 V 1 Ω
IIH,CTRL Input high current, control pins (SEL, OEn) 1 µA
IIL,CTRL Input low current, control pins (SEL, OEn) 1 µA
IIH,HS Input high current, high-speed pins [Ax/Bx/Cx][p/n] VIN = 2 V for selected port, A and B with SEL = 0, and A and C with
SEL = VCC		 1 µA
IIH,HS Input high current, high-speed pins [Ax/Bx/Cx][p/n] VIN = 2 V for non-selected port, C with SEL = 0, and B with
SEL = VCC(1)		 100 140 µA
IIL,HS Input low current, high-speed pins [Ax/Bx/Cx][p/n] 1 µA
(1) There is a 20-kΩ pull-down in non-selected port.

7.6 High-Speed Performance Parameters

PARAMETER TEST CONDITION MIN TYP MAX UNIT
IL Differential insertion loss ƒ = 0.3 MHz –0.5 dB
ƒ = 0.625 MHz -0.55
ƒ = 2.5 GHz –0.8
ƒ = 4 GHz –1.4
ƒ = 5 GHz –1.6
BW –3-dB bandwidth 8 GHz
RL Differential return loss ƒ = 0.3 MHz –25 dB
ƒ = 2.5 GHz –13
ƒ = 4 GHz –13
ƒ = 5 GHz – 12
OIRR Differential OFF isolation ƒ = 0.3 MHz –75 dB
ƒ = 2.5 GHz –23
ƒ = 4 GHz –19
ƒ = 5 GHz –19
XTALK Differential crosstalk ƒ = 0.3 MHz –90 dB
ƒ = 2.5 GHz –35
ƒ = 4 GHz –32.5
ƒ = 5 GHz –32

7.7 Switching Characteristics

PARAMETER MIN TYP MAX UNIT
tPD Switch propagation delay (see Figure 3) 80 ps
tSW_ON Switching time SEL-to-Switch ON (see Figure 2) 0.5 µs
tSW_OFF Switching time SEL-to-Switch OFF (see Figure 2) 0.5 µs
tSK_INTRA Intra-pair output skew (see Figure 3) 6 ps
tSK_INTER Inter-pair output skew (see Figure 3) 20 ps

 
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