SLASE74F May   2015  – September 2016 HD3SS3212

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 High-Speed Performance Parameters
    7. 7.7 Switching Characteristics
  8. 8 Parameter Measurement Information
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1 Output Enable and Power Savings
    4. 9.4 Device Functional Modes
  10. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Applications
      1. 10.2.1 Down Facing Port for USB3.1 Type C
        1. 10.2.1.1 Design Requirements
        2. 10.2.1.2 Detailed Design Procedure
        3. 10.2.1.3 Application Curves
    3. 10.3 Systems Examples
      1. 10.3.1 Up Facing Port for USB3.1 Type C
      2. 10.3.2 PCIE/SATA/USB
      3. 10.3.3 PCIE/eSATA
      4. 10.3.4 USB/eSATA
      5. 10.3.5 MIPI Camera Serial Interface
  11. 11Power Supply Recommendations
  12. 12Layout
    1. 12.1 Layout Guidelines
    2. 12.2 Layout Example
  13. 13Device and Documentation Support
    1. 13.1 Related Links
    2. 13.2 Receiving Notification of Documentation Updates
    3. 13.3 Community Resources
    4. 13.4 Trademarks
    5. 13.5 Electrostatic Discharge Caution
    6. 13.6 Glossary
  14. 14Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • RKS|20
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6 Pin Configuration and Functions

RKS Package
20-Pin VQFN
Top View
HD3SS3212 HD3SS3212I po_LASE74.gif

Pin Functions

PIN TYPE(1) DESCRIPTION
NAME NO.
VCC 6 P 3.3-V power
OEn 2 I Active-low chip enable
L: Normal operation
H: Shutdown
A0p 3 I/O Port A, channel 0, high-speed positive signal
A0n 4 I/O Port A, channel 0, high-speed negative signal
GND 5, 11, 20 G Ground
A1p 7 I/O Port A, channel 1, high-speed positive signal
A1n 8 I/O Port A, channel 1, high-speed negative signal
SEL 9 I Port select pin.
L: Port A to Port B
H: Port A to Port C
C1n 12 I/O Port C, channel 1, high-speed negative signal (connector side)
C1p 13 I/O Port C, channel 1, high-speed positive signal (connector side)
C0n 14 I/O Port C, channel 0, high-speed negative signal (connector side)
C0p 15 I/O Port C, channel 0, high-speed positive signal (connector side)
B1n 16 I/O Port B, channel 1, high-speed negative signal (connector side)
B1p 17 I/O Port B, channel 1, high-speed positive signal (connector side)
B0n 18 I/O Port B, channel 0, high-speed negative signal (connector side)
B0p 19 I/O Port B, channel 0, high-speed positive signal (connector side)
RSVD1 1 O Can be left not connected or can be fed to VCC
RSVD2 10 O
(1) The high-speed data ports incorporate 20-kΩ pulldown resistors that are switched in when a port is not selected and switched out when the port is selected.