SLLSES1D December   2015  – September 2020 HD3SS3220

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
  7. 7 Detailed Description
    1. 7.1 Overview
      1. 7.1.1 Cables, Adapters, and Direct Connect Devices
        1. 7.1.1.1 USB Type-C receptacles and Plugs
        2. 7.1.1.2 USB Type-C Cables
        3. 7.1.1.3 Legacy Cables and Adapters
        4. 7.1.1.4 Direct Connect Device
        5. 7.1.1.5 Audio Adapters
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  DFP/Source – Downstream Facing Port
      2. 7.3.2  UFP/Sink – Upstream Facing Port
      3. 7.3.3  DRP – Dual Role Port
      4. 7.3.4  Cable Orientation and Mux Control
      5. 7.3.5  Type-C Current Mode
      6. 7.3.6  Accessory Support
      7. 7.3.7  Audio Accessory
      8. 7.3.8  Debug Accessory
      9. 7.3.9  VCONN support for Active Cables
      10. 7.3.10 I2C and GPIO Control
      11. 7.3.11 HD3SS3220 V(BUS) Detection
      12. 7.3.12 VDD5 and VCC33 Power-On Requirements
    4. 7.4 Device Functional Modes
      1. 7.4.1 Unattached Mode
      2. 7.4.2 Active Mode
      3. 7.4.3 Dead Battery
      4. 7.4.4 Shutdown Mode
    5. 7.5 Programming
    6. 7.6 Register Maps
      1. 7.6.1 Device Identification Register (offset = 0x07 through 0x00) [reset = 0x00, 0x54, 0x55, 0x53, 0x42, 0x33, 0x32, 0x32]
      2. 7.6.2 Connection Status Register (offset = 0x08) [reset = 0x00]
      3. 7.6.3 Connection Status and Control Register (offset = 0x09) [reset = 0x20]
      4. 7.6.4 General Control Register (offset = 0x0A) [reset = 0x00]
      5. 7.6.5 Device Revision Register (offset = 0xA0) [reset = 0x02]
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application, DRP Port
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Typical Application, DFP Port
        1. 8.2.3.1 Design Requirements
        2. 8.2.3.2 Detailed Design Procedure
      4. 8.2.4 Typical Application, UFP Port
        1. 8.2.4.1 Design Requirements
        2. 8.2.4.2 Detailed Design Procedure
  9. 9 Layout
    1. 9.1 Layout Guidelines
      1. 9.1.1 Suggested PCB Stackups
      2. 9.1.2 High-Speed Signal Trace Length Matching
      3. 9.1.3 Differential Signal Spacing
      4. 9.1.4 High-Speed Differential Signal Rules
      5. 9.1.5 Symmetry in the Differential Pairs
      6. 9.1.6 Via Discontinuity Mitigation
      7. 9.1.7 Surface-Mount Device Pad Discontinuity Mitigation
      8. 9.1.8 ESD/EMI Considerations
    2. 9.2 Layout
  10. 10Device and Documentation Support
    1. 10.1 Receiving Notification of Documentation Updates
    2. 10.2 Community Resources
    3. 10.3 Trademarks
  11. 11Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

Pin Functions

PIN I/O DESCRIPTION
NAME NO.
CC2 1 I/O Type-C Configuration channel signal 2
CC1 2 I/O Type-C Configuration channel signal 1
CURRENT_MODE 3 I Tri-level input pin to indicate current advertisement in DFP (or DFP in DRP) mode while in GPIO mode. Don’t care in UFP mode. Provides the flexibility to advertise higher current without I2C. The pin has 250 K internal pull-down.
L – Low - Default – 900 mA
M - Medium (Install 500 K to VDD5 on the PCB) – 1.5 A
H - High (Install 10 K to VDD5 on the PCB) – 3 A
PORT 4 I Tri-level input pin to indicate port mode. The state of this pin is sampled when HD3SS3220’s ENn_CC is asserted low, and VDD5 is active. This pin is also sampled following a I2C_SOFT_RESET.
H - DFP (Pull-up to VDD5 if DFP mode is desired)
NC - DRP (Leave unconnected if DRP mode is desired)
L - UFP (Pull-down or tie to GND if UFP mode is desired)
VBUS_DET 5 I 5-28V VBUS input voltage. VBUS detection determines UFP attachment. One 900K external resistor required between system VBUS and VBUS_DET pin.
TXp 6 I/O Host/Device USB SuperSpeed differential Signal TX positive
TXn 7 I/O Host/Device USB SuperSpeed differential Signal TX negative
VCC33 8 P 3.3-V Power supply
RXp 9 I/O Host/Device USB SuperSpeed differential Signal RX positive
RXn 10 I/O Host/Device USB SuperSpeed differential Signal RX negative
DIR 11 O Type-C plug orientation. Open drain output.
A pull-up resistor (that is, 200 K) must be installed for proper operation of the device.
ENn_MUX 12 I Active Low MUX Enable:
L - Normal operation, and
H - Shutdown.
GND 13, 28 G Ground
RX1n 14 I/O Type-C Port - USB SuperSpeed differential Signal RX1 negative
RX1p 15 I/O Type-C Port - USB SuperSpeed differential Signal RX1 positive
TX1n 16 I/O Type-C Port - USB SuperSpeed differential Signal TX1 negative
TX1p 17 I/O Type-C Port - USB SuperSpeed differential Signal TX1 positive
RX2n 18 I/O Type-C Port - USB SuperSpeed differential Signal RX2 negative
RX2p 19 I/O Type-C Port - USB SuperSpeed differential Signal RX2 positive
TX2n 20 I/O Type-C Port - USB SuperSpeed differential Signal TX2 negative
TX2p 21 I/O Type-C Port - USB SuperSpeed differential Signal TX2 positive
ADDR 22 I Tri-level input pin to indicate I2C address or GPIO mode:
H (connect to VDD5) - I2C is enabled and I2C 7-bit address is 0x67.
NC - GPIO mode (I2C is disabled)
L (connect to GND) - I2C is enabled and I2C 7-bit address is 0x47.
ADDR pin should be pulled up to VDD5 if high configuration is desired
INT_N/OUT3 23 O The INT_N/OUT3 is a dual-function pin.
When used as the INT_N, the pin is an open drain output in I2C control mode and is an active low interrupt signal for indicating changes in I2C registers.
When used as OUT3, the pin is in audio accessory detect in GPIO mode:
H - no detection, and
L - audio accessory connection detected.
VCONN_FAULT_N 24 O Open drain output. Asserted low when VCONN overcurrent detected.
SDA/OUT1 25 I/O The SDA/OUT1 is a dual-function pin.
When I2C is enabled (ADDR pin is high or low), this pin is the I2C communication data signal.
When in GPIO mode (ADDR pin is NC), this pin is an open drain output for communicating Type-C current mode detect when the device is in UFP mode:
H – Default (900 mA) current mode detected, and
L – Medium (1.5 A) or High (3 A) Current Mode detected.
SCL/OUT2 26 I/O The SCL/OUT2 is a dual function pin.
When I2C is enabled (ADDR pin is high or low), this pin is the I2C communication clock signal.
When in GPIO mode (ADDR pin is NC), this pin is an open drain output for communicating Type-C current mode detect when the device is in UFP mode:
H – Default or Medium current mode detected, and
L – High current mode detected.
ID 27 O Open drain output. Asserted low when CC pin detected device attachment when port is a source (DFP), or dual-role (DRP) acting as source (DFP).
ENn_CC 29 I Enable signal for CC controller. Enable is active low.
VDD5 30 P 5-V Power supply
Thermal Pad – – The thermal PAD must be connected to GND, see the Thermal Pad connection techniques (SLMA002).