SLLSES1D
December 2015 – September 2020
HD3SS3220
PRODUCTION DATA
1
Features
2
Applications
3
Description
4
Revision History
5
Pin Configuration and Functions
Pin Functions
6
Specifications
6.1
Absolute Maximum Ratings
6.2
ESD Ratings
6.3
Recommended Operating Conditions
6.4
Thermal Information
6.5
Electrical Characteristics
6.6
Timing Requirements
7
Detailed Description
7.1
Overview
7.1.1
Cables, Adapters, and Direct Connect Devices
7.1.1.1
USB Type-C receptacles and Plugs
7.1.1.2
USB Type-C Cables
7.1.1.3
Legacy Cables and Adapters
7.1.1.4
Direct Connect Device
7.1.1.5
Audio Adapters
7.2
Functional Block Diagram
7.3
Feature Description
7.3.1
DFP/Source – Downstream Facing Port
7.3.2
UFP/Sink – Upstream Facing Port
7.3.3
DRP – Dual Role Port
7.3.4
Cable Orientation and Mux Control
7.3.5
Type-C Current Mode
7.3.6
Accessory Support
7.3.7
Audio Accessory
7.3.8
Debug Accessory
7.3.9
VCONN support for Active Cables
7.3.10
I2C and GPIO Control
7.3.11
HD3SS3220 V(BUS) Detection
7.3.12
VDD5 and VCC33 Power-On Requirements
7.4
Device Functional Modes
7.4.1
Unattached Mode
7.4.2
Active Mode
7.4.3
Dead Battery
7.4.4
Shutdown Mode
7.5
Programming
7.6
Register Maps
7.6.1
Device Identification Register (offset = 0x07 through 0x00) [reset = 0x00, 0x54, 0x55, 0x53, 0x42, 0x33, 0x32, 0x32]
7.6.2
Connection Status Register (offset = 0x08) [reset = 0x00]
7.6.3
Connection Status and Control Register (offset = 0x09) [reset = 0x20]
7.6.4
General Control Register (offset = 0x0A) [reset = 0x00]
7.6.5
Device Revision Register (offset = 0xA0) [reset = 0x02]
8
Application and Implementation
8.1
Application Information
8.2
Typical Application, DRP Port
8.2.1
Design Requirements
8.2.2
Detailed Design Procedure
8.2.3
Typical Application, DFP Port
8.2.3.1
Design Requirements
8.2.3.2
Detailed Design Procedure
8.2.4
Typical Application, UFP Port
8.2.4.1
Design Requirements
8.2.4.2
Detailed Design Procedure
9
Layout
9.1
Layout Guidelines
9.1.1
Suggested PCB Stackups
9.1.2
High-Speed Signal Trace Length Matching
9.1.3
Differential Signal Spacing
9.1.4
High-Speed Differential Signal Rules
9.1.5
Symmetry in the Differential Pairs
9.1.6
Via Discontinuity Mitigation
9.1.7
Surface-Mount Device Pad Discontinuity Mitigation
9.1.8
ESD/EMI Considerations
9.2
Layout
10
Device and Documentation Support
10.1
Receiving Notification of Documentation Updates
10.2
Community Resources
10.3
Trademarks
11
Mechanical, Packaging, and Orderable Information
Package Options
Mechanical Data (Package|Pins)
RNH|30
MPQF439A
Thermal pad, mechanical data (Package|Pins)
Orderable Information
sllses1d_oa
sllses1d_pm
9.2
Layout
Figure 9-10
Layout Example
Figure 9-11
Layout Example 2