SLLSES1D December   2015  – September 2020 HD3SS3220

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
  7. 7 Detailed Description
    1. 7.1 Overview
      1. 7.1.1 Cables, Adapters, and Direct Connect Devices
        1. 7.1.1.1 USB Type-C receptacles and Plugs
        2. 7.1.1.2 USB Type-C Cables
        3. 7.1.1.3 Legacy Cables and Adapters
        4. 7.1.1.4 Direct Connect Device
        5. 7.1.1.5 Audio Adapters
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  DFP/Source – Downstream Facing Port
      2. 7.3.2  UFP/Sink – Upstream Facing Port
      3. 7.3.3  DRP – Dual Role Port
      4. 7.3.4  Cable Orientation and Mux Control
      5. 7.3.5  Type-C Current Mode
      6. 7.3.6  Accessory Support
      7. 7.3.7  Audio Accessory
      8. 7.3.8  Debug Accessory
      9. 7.3.9  VCONN support for Active Cables
      10. 7.3.10 I2C and GPIO Control
      11. 7.3.11 HD3SS3220 V(BUS) Detection
      12. 7.3.12 VDD5 and VCC33 Power-On Requirements
    4. 7.4 Device Functional Modes
      1. 7.4.1 Unattached Mode
      2. 7.4.2 Active Mode
      3. 7.4.3 Dead Battery
      4. 7.4.4 Shutdown Mode
    5. 7.5 Programming
    6. 7.6 Register Maps
      1. 7.6.1 Device Identification Register (offset = 0x07 through 0x00) [reset = 0x00, 0x54, 0x55, 0x53, 0x42, 0x33, 0x32, 0x32]
      2. 7.6.2 Connection Status Register (offset = 0x08) [reset = 0x00]
      3. 7.6.3 Connection Status and Control Register (offset = 0x09) [reset = 0x20]
      4. 7.6.4 General Control Register (offset = 0x0A) [reset = 0x00]
      5. 7.6.5 Device Revision Register (offset = 0xA0) [reset = 0x02]
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application, DRP Port
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Typical Application, DFP Port
        1. 8.2.3.1 Design Requirements
        2. 8.2.3.2 Detailed Design Procedure
      4. 8.2.4 Typical Application, UFP Port
        1. 8.2.4.1 Design Requirements
        2. 8.2.4.2 Detailed Design Procedure
  9. 9 Layout
    1. 9.1 Layout Guidelines
      1. 9.1.1 Suggested PCB Stackups
      2. 9.1.2 High-Speed Signal Trace Length Matching
      3. 9.1.3 Differential Signal Spacing
      4. 9.1.4 High-Speed Differential Signal Rules
      5. 9.1.5 Symmetry in the Differential Pairs
      6. 9.1.6 Via Discontinuity Mitigation
      7. 9.1.7 Surface-Mount Device Pad Discontinuity Mitigation
      8. 9.1.8 ESD/EMI Considerations
    2. 9.2 Layout
  10. 10Device and Documentation Support
    1. 10.1 Receiving Notification of Documentation Updates
    2. 10.2 Community Resources
    3. 10.3 Trademarks
  11. 11Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6.5 Electrical Characteristics

over operating free-air temperature range (unless otherwise noted)
PARAMETERTEST CONDITIONSMINTYPMAXUNIT
Power Consumption
I(ACTIVE)Current consumption in active mode- both CC controller and SS mux onENn_CC/Mux = L0.70.9mA
ICCCurrent consumption in active mode – CC controller on and SS mux offENn_CC = L, ENn_Mux = H0.2mA
I(SHUTDOWN)Current consumption in shutdown modeENn_CC/Mux = H5µA
CC PINS
R(CC_DB)Pulldown resistor when in dead-battery mode.4.15.16.1kΩ
R(CC_D)Pulldown resistor when in UFP or DRP mode.4.65.15.6kΩ
V(UFP_CC_USB)Voltage level for detecting a DFP attach when configured as a UFP and DFP is advertising default current source capability.0.250.61V
V(UFP_CC_MED)Voltage level for detecting a DFP attach when configured as a UFP and DFP is advertising medium (1.5 A) current source capability.0.71.16V
V(UFP_CC_HIGH)Voltage level for detecting a DFP attach when configured as a UFP and DFP is advertising high (3 A) current source capability.1.312.04V
V(DFP_CC_USB)Voltage level for detecting a UFP attach when configured as a DFP and advertising default current source capability.1.511.61.64V
V(DFP_CC_MED)Voltage level for detecting a UFP attach when configured as a DFP and advertising 1.5-A current source capability.1.511.61.64V
V(DFP_CC_HIGH)Voltage level for detecting a UFP attach when configured as a DFP and advertising 3-A current source capability.2.462.62.74V
V(AC_CC_USB)Voltage level for detecting an active cable attach when configured as a DFP and advertising default current source capability.0.150.20.25V
V(AC_CC_MED)Voltage level for detecting an active cable attach when configured as a DFP and advertising 1.5-A current source capability.0.350.40.45V
V(DFP_CC_HIGH)Voltage level for detecting an active cable attach when configured as a DFP and advertising 3-A current source capability.0.750.80.84V
ICC(DEFAULT_P)Default mode pull-up current source when operating in DFP or DRP mode.648096µA
ICC(MED_P)Medium (1.5 A) mode pull-up current source when operating in DFP or DRP mode.166180194µA
ICC(HIGH_P)High (3 A) mode pull-up current source when operating in DFP or DRP mode.34330356µA
3-Level Input Pins: PORT, ADDR, ENn_CC and CURRENT_MODE
VILLow-level input voltage0.4V
VMMid-Level (Floating) voltage (PORT, ADDR and CURRENT_MODE pins)0.28 x VDD50.56 x VDD5V
VIHHigh-level input voltageVDD5 - 0.3VDD5V
IIHHigh-level input current2020µA
IILLow-level input current–1010µA
IID(LKG)Current Leakage on ID pinVDD5 = 0 V, ID = 5 V10µA
R(pu)Internal pull-up resistance (PORT and ADDR pins)588kΩ
R(pd)Internal pull-down resistance (PORT and ADDR pins)1.1MΩ
R(pd_CURRENT)Internal pull-down resistance (CURRENT_MODE pin)275kΩ
R(ENn_CC)Internal pull-up resistance (ENn_CC pin)1.1MΩ
Input Pins: ENn_MUX
VILLow-level input voltage0.3 x VCC33V
VIHHigh-level input voltage0.7 x VCC33V
IIHHigh-level input current–11µA
IILLow-level input current–11µA
Open Drain Output Pins: OUT1, OUT2, INT_N/OUT3, ID, VCONN_FAULT_N, DIR
VOLLow-level signal output voltageIOL = –1.6 mA0.4V
I2C– SDA/OUT1, SCL/OUT2 can Operate from 1.8/3.3 V (±10%)(1)
VIHHigh-level input voltage1.05V
VILLow-level input voltage0.4V
VOLLow-level output voltage (open-drain)IOL = –1.6 mA0.4V
VBUS_DET IO Pin (Connected to System VBUS Signal)
V(BUS_THR)VBUS threshold range2.953.33.8V
RVBUSExternal resistor between VBUS and VBUS_DET pin855887920KΩ
R(VBUS_DET_INT)Internal pull-down resistor at VBUS_DET pin95kΩ
VCONN
RONOn resistance of the VCONN power FET1.25Ω
V(TOL)Voltage tolerance on VCONN power FET5.5V
V(pass)Voltage to pass through VCONN power FET5.5V
I(VCONN)VCONN current limit. VCONN will be disconnected above this value225300375mA
MUX High Speed Performance Parameters
ILDifferential Insertion Lossf = 0.3 Mhz–0.43dB
f = 2.5 Ghz–1.07
f = 5 Ghz–1.42
BWBandwidth8Ghz
RLDifferential return lossf = 0.3 Mhz–27dB
f = 2.5 Ghz–9
f = 5 Ghz–9
OIRRDifferential OFF isolationf = 0.3 Mhz–79dB
f = 2.5 Ghz–23
f = 5 Ghz–20
XTALKDifferential Cross Talkf = 0.3 Mhz–89dB
f = 2.5 Ghz–34
f = 5 Ghz–30
RONOn resistance8Ω
(1) When using 3.3 V for I2C, customer must ensure VDD5 is above 3 V at all times.