SLAS840C March   2012  – October 2015 HD3SS3415

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Description continued
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Dissipation Ratings
    7. 7.7 Typical Characteristics
  8. 8 Parameter Measurement Information
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
    4. 9.4 Device Functional Modes
  10. 10Application and Implementation
    1. 10.1 Application Information
      1. 10.1.1 AC Coupling Caps
    2. 10.2 Typical Application
      1. 10.2.1 Design Requirements
      2. 10.2.2 Detailed Design Procedure
      3. 10.2.3 Application Curves
  11. 11Power Supply Recommendations
  12. 12Layout
    1. 12.1 Layout Guidelines
    2. 12.2 Layout Example
  13. 13Device and Documentation Support
    1. 13.1 Community Resources
    2. 13.2 Trademarks
    3. 13.3 Electrostatic Discharge Caution
    4. 13.4 Glossary
  14. 14Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

10 Application and Implementation

NOTE

Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality.

10.1 Application Information

10.1.1 AC Coupling Caps

Many interfaces require AC coupling between the transmitter and receiver. The 0402 capacitors are the preferred option to provide AC coupling, and the 0603 size capacitors also work. The 0805 size capacitors and C-packs should be avoided. When placing AC coupling capacitors symmetric placement is best. A capacitor value of 0.1 µF is best and the value should be match for the ± signal pair. The placement should be along the TX pairs on the system board, which are usually routed on the top layer of the board.

There are several placement options for the AC coupling capacitors. Because the switch requires a bias voltage, the capacitors must only be placed on one side of the switch. If they are placed on both sides of the switch, a biasing voltage should be provided. A few placement options are shown below. In Figure 11, the coupling capacitors are placed between the switch and endpoint. In this situation, the switch is biased by the system/host controller.

HD3SS3415 AC_coupled1_las828.png Figure 11. AC Coupling Capacitors Between Switch Tx and Endpoint Tx

In Figure 12, the coupling capacitors are placed on the host transmit pair and endpoint transmit pair. In this situation, the switch on the top is biased by the endpoint and the lower switch is biased by the host controller.

HD3SS3415 AC_coupled2_las828.png Figure 12. AC Coupling Capacitors on Host Tx and Endpoint Tx

If the common-mode voltage in the system is higher than 2 V, the coupling capacitors are placed on both sides of the switch (shown in Figure 13). A biasing voltage of less than 2 V is required in this case.

HD3SS3415 AC_coupled3_las828.png Figure 13. AC Coupling Capacitors on Both Sides of Switch

10.2 Typical Application

HD3SS3415 typ_app_las840.gif Figure 14. Typical Application Schematic

10.2.1 Design Requirements

Table 3 lists the design parameters of this example.

Table 3. Design Parameters

DESIGN PARAMETER EXAMPLE VALUE
Input voltage range 3.3 V
Decoupling capacitors 0.1 µF
AC Capacitors 75 nF - 200 nF (100 nF shown) USBSS TX p and n lines require AC capacotprs. Alternate mode signals may or may not require AC capacitors

10.2.2 Detailed Design Procedure

  • Connect VDD and GND pins to the power and ground planes of the printed circuit board, with a 0.1-uF bypass capacitor.
  • Use +3.3-V TTL/CMOS logic level at SEL
  • Use controlled-impedance transmission media for all the differential signals
  • Ensure the received complimentary signals are with a differential amplitude of <1800 mVpp and a common-mode voltage of <2 V

10.2.3 Application Curves

HD3SS3415 source_eye_10Gbps_las840.gif Figure 15. 10 Gbps Source Eye Diagram at A: VID = 800 mVpp; 27-1 PRBS; VCM = 0 V
HD3SS3415 output_eye_10Gbps_las840.gif Figure 16. 10 Gbps Output Eye Diagram at A:
VID = 800 mVpp; 27-1 PRBS; VCM = 0 V; VDD = 3.3 V; SEL = 0 V