SNAS693D July   2017  β€“ February 2021 HDC2010

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Revision History
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 I2C Interface Timing Requirements
    7. 6.7 I2C Interface Electrical Characteristics
    8. 6.8 Typical Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Sleep Mode Power Consumption
      2. 7.3.2 Measurement Modes: Trigger on Demand vs. Auto Measurement
      3. 7.3.3 Heater
      4. 7.3.4 Interrupt Description
        1. 7.3.4.1 DRDY
      5. 7.3.5 INTERRUPT on Threshold
        1. 7.3.5.1 Temperature High
        2. 7.3.5.2 Temperature Low
        3. 7.3.5.3 Humidity High
        4. 7.3.5.4 Humidity Low
    4. 7.4 Device Functional Modes
      1. 7.4.1 Sleep Mode vs. Measurement Mode
    5. 7.5 Programming
      1. 7.5.1 I2C Serial Bus Address Configuration
      2. 7.5.2 I2C Interface
      3. 7.5.3 Serial Bus Address
      4. 7.5.4 Read and Write Operations
    6. 7.6 Register Maps
      1. 7.6.1  Address 0x00 Temperature LSB
      2. 7.6.2  Address 0x01 Temperature MSB
      3. 7.6.3  Address 0x02 Humidity LSB
      4. 7.6.4  Address 0x03 Humidity MSB
      5. 7.6.5  Address 0x04 Interrupt DRDY
      6. 7.6.6  Address 0x05 Temperature MAX
      7. 7.6.7  Address 0x06 Humidity MAX
      8. 7.6.8  Address 0x07 Interrupt Configuration
      9. 7.6.9  Address 0x08 Temperature Offset Adjustment
      10. 7.6.10 47
      11. 7.6.11 Address 0x09 Humidity Offset Adjustment
      12. 7.6.12 49
      13. 7.6.13 Address 0x0A Temperature Threshold LOW
      14. 7.6.14 Address 0x0B Temperature Threshold HIGH
      15. 7.6.15 Address 0x0C Humidity Threshold LOW
      16. 7.6.16 Address 0x0D Humidity Threshold HIGH
      17. 7.6.17 Address 0x0E Reset and DRDY/INT Configuration Register
      18. 7.6.18 Address 0x0F Measurement Configuration
      19. 7.6.19 Manufacturer ID Low
      20. 7.6.20 Manufacturer ID High
      21. 7.6.21 Device ID Low
      22. 7.6.22 Device ID High
  9. 8  Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curve
  10. 9 Power Supply Recommendations
  11. 10Layout
    1. 10.1 Layout Guidelines
      1. 10.1.1 Guidelines for HDC2010 Storage and PCB Assembly
        1. 10.1.1.1 Storage and Handling
        2. 10.1.1.2 Soldering Reflow
        3. 10.1.1.3 Rework
        4. 10.1.1.4 High Temperature and Humidity Exposure
        5. 10.1.1.5 Bake/Re-Hydration Procedure
    2. 10.2 Layout Example
  12. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 Receiving Notification of Documentation Updates
    3. 11.3 Support Resources
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  13. 12Mechanical, Packaging, and Orderable Information
    1. 12.1 Tape and Reel Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • YPA|6
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7.3.4 Interrupt Description

Note:

When multiple bits are enabled, the DRDY/INT pin can only reflect the status of one interrupt bit at a time. The DRDY/INT pin DOES NOT function as the logical β€˜OR’ of interrupt bits that have been enabled.

The highest priority is given to TH_ENABLE bit, followed by TL_ENABLE, HH_ENABLE, and HL_ENABLE bits in descending order. Therefore, programming recommendations are provided as below:

  • The DRDY/INT will track the HL_ENABLE if enabled and all other ENABLE bits are disabled.
  • The DRDY/INT will track the HH_ENABLE if enabled and the TH_ENABLE and TL_ENABLE are disabled.
  • The DRDY/INT will track the TL_ENABLE if enabled and the TH_ENABLE is disabled.
  • The DRDY/INT will track the TH_ENABLE if enabled and is independent of other ENABLE bit settings.