SNAS693D July 2017 – February 2021 HDC2010
PRODUCTION DATA
Refer to the PDF data sheet for device specific package drawings
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
DRDY_STATUS | TH_STATUS | TL_STATUS | HH_STATUS | HL_STATUS | RES | RES | RES |
BIT | FIELD | TYPE | RESET | DESCRIPTION |
---|---|---|---|---|
7 | DRDY_STATUS | R/W | 0 | DataReady bit status 0 = Data Not Ready 1 = Data Ready DRDY_STATUS is cleared to 0 when read |
6 | TH_STATUS | R/W | 0 | Temperature threshold HIGH Interrupt status 0 = No interrupt 1 = Interrupt TH_STATUS is cleared to 0 when read |
5 | TL_STATUS | R/W | 0 | Temperature threshold LOW Interrupt status 0 = No interrupt 1 = Interrupt TL_STATUS is cleared to 0 when read |
4 | HH_STATUS | R/W | 0 | Humidity threshold HIGH Interrupt status 0 = No interrupt 1 = Interrupt HH_STATUS is cleared to 0 when read |
3 | HL_STATUS | R/W | 0 | Humidity threshold LOW Interrupt status 0 = No interrupt 1 = Interrupt HL_STATUS is cleared to 0 when read |
2 | RES | 0 | Reserved | |
1 | RES | 0 | Reserved | |
0 | RES | 0 | Reserved |
DRDY_STATUS indicates that temperature and/or humidity conversion is terminated. This bit is cleared when the Interrupt/DRDY register is read or the output registers TEMPERATURE_HIGH, TEMPERATURE_LOW, HUMIDITY_HIGH and HUMIDITY_LOW are read.
The TL_STATUS indicates that the Temperature Threshold LOW value is exceeded. The behavior is defined by 0x0E Configuration register value. The bit is cleared when the register Interrupt DRDY is read.
The TH_STATUS indicates that the Temperature Threshold HIGH value is exceeded. The behavior is defined by 0x0E Configuration register value. The bit is cleared when the register Interrupt DRDY is read.
The HH_STATUS indicates that the Humidity Threshold HIGH value is exceeded. The behavior is defined by 0x0E Configuration register value. The bit is cleared when the register Interrupt DRDY is read.
The HL_STATUS indicates that the Humidity Threshold LOW value is exceeded. The behavior is defined by 0x0E Configuration register value. The bit is cleared when the register Interrupt DRDY is read.
DRDY/INT pin behaves like the STATUS bits based on the 0x0E Configuration register value.