SNAS693D July 2017 – February 2021 HDC2010
PRODUCTION DATA
Refer to the PDF data sheet for device specific package drawings
When TH_ENABLE is enabled and the temperature is over the programmed threshold level stored in the Temperature Threshold HIGH register, the TH_STATUS bit asserts to 1. The polarity and interrupt mode of the TH_STATUS bit and the DRDY/INT pin can be configured through the INT_POL and INT_MODE bits of Register 0x0E.
The INT_MODE bit sets the threshold to either comparator mode or a level sensitive alarm.
When INT_MODE is set to 1 the TH_STATUS bit is based on the current temperature conversion. The polarity of the DRDY/INT pin is set by INT_POL.
When INT_MODE is set to 0 the TH_STATUS bit remains set to 1 until it is read. The polarity of the DRDY/INT pin is set by INT_POL