SNAS817D June 2021 – November 2024 HDC3020-Q1 , HDC3021-Q1 , HDC3022-Q1
PRODUCTION DATA
Refer to the PDF data sheet for device specific package drawings
An I2C controller communicates to a desired target device through a target address byte. The target address byte consists of seven address bits and a direction bit that indicates the intent to execute a read or write operation. The HDC302x-Q1 features two address pins, which allows for supporting four addressable HDC302x-Q1 devices on a single I2C bus. Table 7-2 describes the pin logic levels used to communicate up to four devices.
ADDR | ADDR1 | ADDRESS (7-bit Hex Representation) |
---|---|---|
GND | GND | 0x44 |
GND | VDD | 0x46 |
VDD | GND | 0x45 |
VDD | VDD | 0x47 |