SLLSEC4B June   2013  – August 2016 HVDA551-Q1 , HVDA553-Q1

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Switching Characteristics
    7. 6.7 Typical Characteristic
  7. 7 Parameter Measurement Information
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagrams
    3. 8.3 Feature Description
      1. 8.3.1 Digital Inputs and Outputs
      2. 8.3.2 Using the HVDA553 With Split Termination
      3. 8.3.3 Protection Features
        1. 8.3.3.1 TXD Dominant State Time Out
        2. 8.3.3.2 Thermal Shutdown
        3. 8.3.3.3 Undervoltage Lockout or Unpowered Device
        4. 8.3.3.4 Floating Pins
        5. 8.3.3.5 CAN Bus Short-Circuit Current Limiting
    4. 8.4 Device Functional Modes
      1. 8.4.1 Bus States by Mode
      2. 8.4.2 Normal Mode
      3. 8.4.3 Standby Mode With RXD Wake-Up Request
        1. 8.4.3.1 RXD Wake-Up Request Lockout for Bus-Stuck Dominant Fault (HVDA551)
      4. 8.4.4 Driver and Receiver Function Tables
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Applications
      1. 9.2.1 3.3-V I/O Voltage Level in Low-Power Mode
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
          1. 9.2.1.2.1 Loop Propagation Delay
        3. 9.2.1.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Documentation Support
      1. 12.1.1 Related Documentation
    2. 12.2 Related Links
    3. 12.3 Receiving Notification of Documentation Updates
    4. 12.4 Community Resource
    5. 12.5 Trademarks
    6. 12.6 Electrostatic Discharge Caution
    7. 12.7 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7 Parameter Measurement Information

HVDA551-Q1 HVDA553-Q1 55x_DRIVER_CIRCUIT.gif Figure 2. Driver Voltage, Current, and Test Definition
HVDA551-Q1 HVDA553-Q1 55X_VOUT_DOM_TEST.gif Figure 3. Driver VOD Test Circuit
HVDA551-Q1 HVDA553-Q1 55X_DRIVER_VOLTAGE_TEST.gif
A. The input pulse is supplied by a generator having the following characteristics: PRR ≤ 125 kHz, 50% duty cycle, tr ≤ 6 ns, tf ≤ 6 ns, ZO = 50 Ω.
B. CL includes instrumentation and fixture capacitance within ±20%.
C. For HVDA553 device versions, VIO = VCC.
Figure 4. Driver Test Circuit and Voltage Waveforms
HVDA551-Q1 HVDA553-Q1 rx_v_cd_lls753.gif Figure 5. Receiver Voltage and Current Definitions
HVDA551-Q1 HVDA553-Q1 55X_RECEIVER_TEST.gif
A. The input pulse is supplied by a generator having the following characteristics: PRR ≤ 125 kHz, 50% duty cycle, tr ≤ 6 ns, tf ≤ 6 ns, ZO = 50 Ω.
B. CL includes instrumentation and fixture capacitance within ±20%.
C. For HVDA553 device versions VIO = VCC.
Figure 6. Receiver Test Circuit and Voltage Waveforms

Table 1. Differential Input Voltage Threshold Test

INPUT OUTPUT
VCANH VCANL |VID| R
–11.1 V –12 V 900 mV L VOL
12 V 11.1 V 900 mV L
–6 V –12 V 6 V L
12 V 6 V 6 V L
–11.5 V –12 V 500 mV H VOH
12 V 11.5 V 500 mV H
–12 V –6 V 6 V H
6 V 12 V 6 V H
Open Open X H
HVDA551-Q1 HVDA553-Q1 55X_ENABLE_TEST.gif
A. CL = 100 pF includes instrumentation and fixture capacitance within ±20%.
B. All VI input pulses are from 0 V to VIO and supplied by a generator having the following characteristics: tr or tf ≤ 6 ns. Pulse repetition rate (PRR) = 25 kHz, 50% duty cycle.
C. For HVDA553 device versions, VIO = VCC.
Figure 7. tEN Test Circuit and Waveforms
HVDA551-Q1 HVDA553-Q1 55X_CM_OUT_TEST.gif
A. All VI input pulses are from 0 V to VIO and supplied by a generator having the following characteristics: tr or tf ≤ 6 ns. Pulse repetition rate (PRR) = 125 kHz, 50% duty cycle.
Figure 8. Common-Mode Output Voltage Test and Waveforms
HVDA551-Q1 HVDA553-Q1 55X_TLOOP_TEST.gif
A. CL = 100 pF includes instrumentation and fixture capacitance within ±20%.
B. All VI input pulses are from 0 V to VIO and supplied by a generator having the following characteristics: tr or tf ≤ 6 ns. Pulse repetition rate (PRR) = 125 kHz, 50% duty cycle.
C. For HVDA553 device versions, VIO = VCC.
Figure 9. tPROP(LOOP) Test Circuit and Waveform
HVDA551-Q1 HVDA553-Q1 55X_DST_TEST.gif
A. CL = 100 pF includes instrumentation and fixture capacitance within ±20%.
B. All VI input pulses are from 0 V to VIO and supplied by a generator having the following characteristics: tr or tf ≤ 6 ns. Pulse repetition rate (PRR) = 500 Hz, 50% duty cycle.
C. For HVDA553 device versions, VIO = VCC.
Figure 10. TXD Dominant Time-Out Test Circuit and Waveforms
HVDA551-Q1 HVDA553-Q1 55X_DRIVER_SHORT_TEST.gif
A. For HVDA553 device versions VIO = VCC.
Figure 11. Driver Short-Circuit Current Test and Waveforms
HVDA551-Q1 HVDA553-Q1 55X_DRIVE_OUT_SYM_TEST.gif
A. All VI input pulses are from 0 V to VIO and supplied by a generator having the following characteristics: tr and tf ≤ 6 ns, pulse repetition rate (PRR) = 250 kHz, 50% duty cycle.
Figure 12. Driver Output Symmetry Test Circuit