SLLSEC4B June   2013  – August 2016 HVDA551-Q1 , HVDA553-Q1

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Switching Characteristics
    7. 6.7 Typical Characteristic
  7. 7 Parameter Measurement Information
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagrams
    3. 8.3 Feature Description
      1. 8.3.1 Digital Inputs and Outputs
      2. 8.3.2 Using the HVDA553 With Split Termination
      3. 8.3.3 Protection Features
        1. 8.3.3.1 TXD Dominant State Time Out
        2. 8.3.3.2 Thermal Shutdown
        3. 8.3.3.3 Undervoltage Lockout or Unpowered Device
        4. 8.3.3.4 Floating Pins
        5. 8.3.3.5 CAN Bus Short-Circuit Current Limiting
    4. 8.4 Device Functional Modes
      1. 8.4.1 Bus States by Mode
      2. 8.4.2 Normal Mode
      3. 8.4.3 Standby Mode With RXD Wake-Up Request
        1. 8.4.3.1 RXD Wake-Up Request Lockout for Bus-Stuck Dominant Fault (HVDA551)
      4. 8.4.4 Driver and Receiver Function Tables
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Applications
      1. 9.2.1 3.3-V I/O Voltage Level in Low-Power Mode
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
          1. 9.2.1.2.1 Loop Propagation Delay
        3. 9.2.1.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Documentation Support
      1. 12.1.1 Related Documentation
    2. 12.2 Related Links
    3. 12.3 Receiving Notification of Documentation Updates
    4. 12.4 Community Resource
    5. 12.5 Trademarks
    6. 12.6 Electrostatic Discharge Caution
    7. 12.7 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

5 Pin Configuration and Functions

HVDA551 D Package
8-Pin SOIC
Top View
HVDA553 D Package
8-Pin SOIC
Top View

Pin Functions

PIN TYPE(1) DESCRIPTION
NO. NAME
1 TXD I CAN transmit data input (low for dominant bus state, high for recessive bus state)
2 GND G Ground connection
3 VCC P Transceiver 5-V supply voltage
4 RXD O CAN receive data output (low in dominant bus state, high in recessive bus state)
5 VIO (HVDA551) P/O Transceiver logic level (IO) supply voltage
SPLIT (HVDA553) P/O Common-mode stabilization output
6 CANL I/O Low level CAN bus line
7 CANH I/O High level CAN bus line
8 STB I Standby mode select pin (active high)
(1) G = Ground, I = Input, O = Output, and P = Power