Refer to the PDF data sheet for device specific package drawings
The INA114 is a low-cost, general-purpose instrumentation amplifier offering excellent accuracy. The versatile three-op-amp design and small size make this device an excellent choice for a wide range of applications.
A single external resistor sets any gain from 1 to 10,000. Internal input protection withstands up to ±40V without damage.
The INA114 is laser trimmed for very low offset voltage (50µV), low drift (0.3µV/°C), and high common-mode rejection (115dB at G = 1000). The device operates with power supplies as low as ±2.25V, allowing use in battery-operated and single 5V supply systems.
The INA114 is available in 8-pin PDIP and 16-pin SOIC surface-mount packages. Both are specified for a temperature range of −40°C to +85°C.
PART NUMBER | PACKAGE(1) | PACKAGE SIZE(2) |
---|---|---|
INA114 | P (PDIP, 8) | 9.81mm × 9.43mm |
DW (SOIC, 16) | 10.3mm × 10.3mm |
MIN | MAX | UNIT | |||
---|---|---|---|---|---|
VS | Supply voltage | Single supply, VS = (+VS) | 36 | V | |
Dual supply, VS = (+VS) – (–VS) | –18 | 18 | V | ||
Signal input pins | –40 | 40 | V | ||
VO | Signal output voltage | (–VS) – 0.5 | (+VS) + 0.5 | V | |
IS | Output short-circuit (to VS/2) | Continuous | |||
TA | Operating temperature | –40 | 125 | °C | |
TJ | Junction temperature | 150 | °C | ||
Tstg | Storage temperature | –40 | 125 | °C |
VALUE | UNIT | |||
---|---|---|---|---|
V(ESD) | Electrostatic discharge | Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) | ±1500 | V |
Charged-device model (CDM), per ANSI/ESDA/JEDEC JS-002(2) | ±1500 |
MIN | MAX | UNIT | |||
---|---|---|---|---|---|
VS | Supply voltage | Single supply, VS = (+VS) | 4.5 | 36 | V |
Dual supply, VS = (+VS) – (–VS) | ±2.25 | ±18 | |||
TA | Specified temperature | –40 | 85 | °C |
THERMAL METRIC(1) | INA114 | UNIT | ||
---|---|---|---|---|
DW (SOIC) | P (PDIP) | |||
16 PINS | 8 PINS | |||
RθJA | Junction-to-ambient thermal resistance | 74.2 | 110.2 | ℃/W |
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |||
---|---|---|---|---|---|---|---|---|
INPUT | ||||||||
VOS | Offset voltage | RTI | INA114BP, BU | ±10 + 20/G | ±50 + 150/G | µV | ||
INA114AP, AU | ±25 + 30/G | ±125 + 500/G | ||||||
Offset voltage drift | TA = –40°C to +85°C, RTI | INA114BP, BU | ±0.1 + 0.5/G | ±0.3 + 5/G | µV/℃ | |||
INA114AP, AU | ±0.25 + 5/G | ±1 + 10/G | ||||||
Long-term stability | ±0.2 + 0.5/G | µV/mo | ||||||
Differential impedance | 100 || 6 | GΩ || pF | ||||||
Common-mode impedance | 100 || 6 | GΩ || pF | ||||||
Operating input voltage | (V–) + 4 | (V+) – 4 | V | |||||
PSRR | Power-supply rejection ratio | RTI, ±2.25V to ±18V | 0.5 + 2/G | 3 + 10/G | µV/V | |||
CMRR | Common-mode rejection ratio | At dc to 60Hz, RTI, VCM = ±10V, ΔRS = 1kΩ |
G = 1 | INA114BP, BU | 80 | 96 | dB | |
INA114AP, AU | 75 | 90 | dB | |||||
G = 10 | INA114BP, BU | 96 | 115 | |||||
INA114AP, AU | 90 | 106 | ||||||
G = 100 | INA114BP, BU | 110 | 120 | |||||
INA114AP, AU | 106 | 110 | ||||||
G = 1000 | INA114BP, BU | 115 | 120 | |||||
INA114AP, AU | 106 | 110 | ||||||
BIAS CURRENT | ||||||||
IB | Input bias current | VCM = VS / 2 | INA114BP, BU | ±0.5 | ±2 | nA | ||
INA114AP, AU | ±0.5 | ±5 | ||||||
Input bias current drift | TA = –40°C to +85°C | INA114BP, BU | ±8 | pA/℃ | ||||
INA114AP, AU | ±8 | |||||||
IOS | Input offset current | VCM = VS / 2 | INA114BP, BU | ±0.5 | ±2 | nA | ||
INA114AP, AU | ±0.5 | ±5 | ||||||
Input offset current drift | TA = –40°C to +85°C | INA114BP, BU | ±8 | pA/℃ | ||||
INA114AP, AU | ±8 | |||||||
NOISE VOLTAGE | ||||||||
Voltage noise | G = 1000, RS = 0Ω | f = 10Hz | 15 | nV/√Hz | ||||
f = 100Hz | 11 | |||||||
f = 1kHz | 11 | |||||||
fB = 0.1Hz to 10Hz | 0.4 | µVPP | ||||||
Noise current | f = 10Hz | 0.4 | pA/√Hz | |||||
f = 1kHz | 0.2 | pA/√Hz | ||||||
fB = 0.1Hz to 10Hz | 18 | pAPP | ||||||
GAIN | ||||||||
G | Gain equation | 1 + (50kΩ / RG) | V/V | |||||
Range of gain | 1 | 10000 | V/V | |||||
GE | Gain error | VO = ±10V, G = 1 | ±0.01 | ±0.05 | % | |||
VO = ±10V | G = 10 | INA114BP, BU | ±0.02 | ±0.4 | ||||
INA114AP, AU | ±0.02 | ±0.5 | ||||||
G = 100 | INA114BP, BU | ±0.05 | ±0.5 | |||||
INA114AP, AU | ±0.05 | ±0.7 | ||||||
G = 1000 | INA114BP, BU | ±0.5 | ±1 | |||||
INA114AP, AU | ±0.5 | ±2 | ||||||
Gain drift | ±2 | ±10 | ppm/°C | |||||
RS = 50kΩ(1) | ±25 | ±100 | ||||||
Gain nonlinearity | VO = –10V to +10V | G = 1 | INA114BP, BU | ±0.0001 | ±0.001 | % of FSR | ||
INA114AP, AU | ±0.0001 | ±0.002 | ||||||
G = 10, 100 | INA114BP, BU | ±0.0005 | ±0.002 | |||||
INA114AP, AU | ±0.0005 | ±0.004 | ||||||
G = 1000 | INA114BP, BU | ±0.002 | ±0.01 | |||||
INA114AP, AU | ±0.002 | ±0.02 | ||||||
OUTPUT | ||||||||
Output voltage | IO = 5mA, TA = –40°C to 85°C | (V–) +1.5 | (V+) –1.5 | V | ||||
VS = ±11.4V | (V–) + 1.4 | (V+) – 1.4 | ||||||
VS = ±2.25V | (V–) +1 | (V+) – 1 | ||||||
Load capacitance stability | 1000 | pF | ||||||
ISC | Short-circuit current | Continuous to VS / 2 | +20 / –15 | mA | ||||
FREQUENCY RESPONSE | ||||||||
BW | Bandwidth, –3dB | G = 1 | 1 | MHz | ||||
G = 10 | 100 | kHz | ||||||
G = 100 | 10 | |||||||
G = 1000 | 1 | |||||||
SR | Slew rate | G = 10, VO = ±10V | 0.3 | 0.6 | V/µs | |||
tS | Settling time | 0.01%, VSTEP = 10V | G = 1 | 18 | µs | |||
G = 10 | 20 | |||||||
G = 100 | 120 | |||||||
G = 1000 | 1100 | |||||||
Overload recovery | 50% overdrive | 20 | µs | |||||
POWER SUPPLY | ||||||||
IQ | Quiescent current | VS = ±2.25V to ±18V, VIN = 0V | ±2.2 | ±3 | mA |
at TA = +25°C, VS = ±15V, G = 1V/V (unless otherwise noted)
RL = 2kΩ |
G = 1 |
G = 1000 |
RL = 2kΩ |
G = 1 |
G = 1000 |
Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes, as well as validating and testing their design implementation to confirm system functionality.
Figure 6-1 shows the basic connections required for operation of the INA114. Applications with noisy or high-impedance power supplies can require decoupling capacitors close to the device pins as shown.
The output is referred to the output reference (Ref) pin, which is normally grounded. This connection must be low-impedance to provide good common-mode rejection. A resistance of 5Ω in series with the Ref pin causes a typical device to degrade to approximately 80dB CMR (G = 1).
Gain of the INA114 is set by connecting a single external resistor, RG:
Figure 6-1 shows commonly used gains and resistor values.
The 50‑kΩ term in Equation 1 comes from the sum of the two internal feedback resistors. These resistors are on-chip metal film resistors which are laser trimmed to accurate absolute values. The accuracy and temperature coefficient of these resistors are included in the gain accuracy and drift specifications of the INA114.
The stability and temperature drift of the external gain setting resistor, RG, also affects gain. The contribution of RG to gain accuracy and drift is directly inferred from the gain Equation 1. Low resistor values required for high gain can make wiring resistance important. Sockets add to the wiring resistance, which contributes additional gain error (possibly an unstable gain error) in gains of approximately 100 or greater.
The INA114 provides very low noise in most applications. For differential source impedances less than 1kΩ, the INA103 can provide lower noise. For source impedances greater than 50kΩ, the INA111 FET-input instrumentation amplifier can provide lower noise.
Low frequency noise of the INA114 is approximately 0.4µVPP measured from 0.1Hz to 10Hz. This noise is approximately one-tenth the noise of low noise chopper-stabilized amplifiers.
The INA114 is laser trimmed for very low offset voltage and drift. Most applications require no external offset adjustment. Figure 6-2 shows an optional circuit for trimming the output offset voltage. The voltage applied to the Ref pin is summed at the output. Maintain low impedance at this node to maintain good common-mode rejection by buffering trim voltage with an op amp as shown.
The input impedance of the INA114 is extremely high-approximately 1010Ω. However, a path must be provided for the input bias current of both inputs. This input bias current is typically less than ±1nA, and can be either polarity as a result of cancellation circuitry. High input impedance means that this input bias current changes very little with varying input voltage.
Input circuitry must provide a path for this input bias current if the INA114 is to operate properly. Figure 6-3 shows various provisions for an input bias current path. Without a bias current return path, the inputs float to a potential that exceeds the common-mode range of the INA114 and the input amplifiers saturate. If the differential source resistance is low, the bias current return path can be connected to one input (see thermocouple example in Figure 6-3). With higher source impedance, use two resistors to provide a balanced input, with the possible advantages of lower input offset voltage due to bias current and better common-mode rejection.
The linear common-mode range of the input op amps of the INA114 is approximately ±13.75V (or 1.25V from the power supplies). As the output voltage increases, however, the linear input range is limited by the output voltage swing of the input amplifiers, A1 and A2. The common-mode range is related to the output voltage of the complete amplifier—see typical characteristic curve Input Common-Mode Range vs Output Voltage.
A combination of common-mode and differential input signals can cause the output of A1 or A2 to saturate. Figure 6-4 shows the output voltage swing of A1 and A2 expressed in terms of a common-mode and differential input voltages. Output swing capability of these internal amplifiers is the same as the output amplifier, A3. For applications where input common-mode range must be maximized, limit the output voltage swing by connecting the INA114 in a lower gain (see performance curve Input Common-Mode Voltage Range vs Output Voltage). If necessary, add gain after the INA114 to increase the voltage swing.
Input overload often produces an output voltage that appears normal. For example, an input voltage of 20V on one input and 40V on the other input obviously exceeds the linear common-mode range of both input amplifiers. Both input amplifiers are saturated to nearly the same output voltage limit; therefore, the difference voltage measured by the output amplifier is near zero. The output of the INA114 is near 0V even though both inputs are overloaded.
The inputs of the INA114 are individually protected for voltages up to ±40V. For example, a condition of –40V on one input and +40V on the other input does not cause damage. Internal circuitry on each input provides low series impedance under normal signal conditions. To provide equivalent protection, series input resistors contribute excessive noise. If the input is overloaded, the protection circuitry limits the input current to a safe value (approximately 1.5mA). Typical performance curve Input Bias Current vs Common-Mode Input Voltage shows this input current limit behavior. The inputs are protected even if no power supply voltage is present.
The surface-mount version of the INA114 has a separate output sense feedback connection (pin 12). Pin 12 must be connected to the output terminal (pin 11) for proper operation. (This connection is made internally on the DIP version of the INA114.)
The output sense connection can be used to sense the output voltage directly at the load for best accuracy. Figure 6-5 shows how to drive a load through series interconnection resistance. Remotely located feedback paths can cause instability. This instability can be generally be eliminated with a high-frequency feedback path through C1. Drive heavy loads or long lines by connecting a buffer inside the feedback path (see Figure 6-6).
TI offers an extensive line of development tools. Tools and software to evaluate the performance of the device, generate code, and develop solutions are listed below.
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This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. | |
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. |