SBOS027C September   2000  – September 2022 INA118

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
    4. 8.4 Device Functional Modes
      1. 8.4.1 Noise Performance
      2. 8.4.2 Input Common-Mode Range
      3. 8.4.3 Input Protection
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Setting the Gain
        2. 9.2.2.2 Dynamic Performance
        3. 9.2.2.3 Offset Trimming
        4. 9.2.2.4 Input Bias Current Return Path
      3. 9.2.3 Application Curves
    3. 9.3 Power Supply Recommendations
      1. 9.3.1 Low-Voltage Operation
      2. 9.3.2 Single-Supply Operation
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
      2. 9.4.2 Layout Example
  10. 10Device and Documentation Support
    1. 10.1 Device Support
      1. 10.1.1 Development Support
    2. 10.2 Receiving Notification of Documentation Updates
    3. 10.3 Support Resources
    4. 10.4 Trademarks
    5. 10.5 Electrostatic Discharge Caution
    6. 10.6 Glossary
  11. 11Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

8.1 Overview

Section 8.2 shows a simplified representation of the INA118 and provides insight into device operation. Each input is protected by two FET transistors that provide a low series resistance under normal signal conditions, thus preserving excellent noise performance. When excessive voltage is applied, these transistors limit input current to approximately 6 mA.

The differential input voltage is buffered by Q1 and Q2 and impressed across RG, causing a signal current to flow through RG, R1, and R2. The output difference amp, A3, removes the common-mode component of the input signal and refers the output signal to the Ref pin.