SBOS632 September   2015 INA188

UNLESS OTHERWISE NOTED, this document contains PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics: VS = ±4 V to ±18 V (VS = 8 V to 36 V)
    6. 6.6 Electrical Characteristics: VS = ±2 V to < ±4 V (VS = 4 V to < 8 V)
    7. 6.7 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Inside the INA188
      2. 7.3.2 Setting the Gain
        1. 7.3.2.1 Gain Drift
      3. 7.3.3 Zero Drift Topology
        1. 7.3.3.1 Internal Offset Correction
        2. 7.3.3.2 Noise Performance
        3. 7.3.3.3 Input Bias Current Clock Feedthrough
      4. 7.3.4 EMI Rejection
      5. 7.3.5 Input Protection and Electrical Overstress
      6. 7.3.6 Input Common-Mode Range
    4. 7.4 Device Functional Modes
      1. 7.4.1 Single-Supply Operation
      2. 7.4.2 Offset Trimming
      3. 7.4.3 Input Bias Current Return Path
      4. 7.4.4 Driving the Reference Pin
      5. 7.4.5 Error Sources Example
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curve
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Development Support
    2. 11.2 Documentation Support
      1. 11.2.1 Related Documentation
    3. 11.3 Community Resources
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

10 Layout

10.1 Layout Guidelines

Attention to good layout practices is always recommended. For best operational performance of the device, use good printed circuit board (PCB) layout practices, including:

  • Care must be taken to ensure that both input paths are well-matched for source impedance and capacitance to avoid converting common-mode signals into differential signals. In addition, parasitic capacitance at the gain-setting pins can also affect CMRR over frequency. For example, in applications that implement gain switching using switches or PhotoMOS® relays to change the value of RG, select the component so that the switch capacitance is as small as possible.
  • Noise can propagate into analog circuitry through the power pins of the circuit as a whole and of the device itself. Bypass capacitors are used to reduce the coupled noise by providing low-impedance power sources local to the analog circuitry.
    • Connect low-ESR, 0.1-μF ceramic bypass capacitors between each supply pin and ground, placed as close to the device as possible. A single bypass capacitor from V+ to ground is applicable for single-supply applications.
  • Separate grounding for analog and digital portions of the circuitry is one of the simplest and most effective methods of noise suppression. One or more layers on multilayer PCBs are usually devoted to ground planes. A ground plane helps distribute heat and reduces EMI noise pickup. Make sure to physically separate digital and analog grounds, paying attention to the flow of the ground current. For more detailed information, see SLOA089, Circuit Board Layout Techniques.
  • In order to reduce parasitic coupling, run the input traces as far away from the supply or output traces as possible. If these traces cannot be kept separate, crossing the sensitive trace perpendicular is much better than in parallel with the noisy trace.
  • Place the external components as close to the device as possible. As illustrated in Figure 57, keeping RG close to the pins minimizes parasitic capacitance.
  • Keep the traces as short as possible.

10.2 Layout Example

INA188 layout_example_bos501.gif Figure 57. PCB Layout Example