SBOS743B July   2015  – September 2024 INA226-Q1

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 Basic ADC Functions
        1. 6.3.1.1 Power Calculation
        2. 6.3.1.2 Alert Pin
    4. 6.4 Device Functional Modes
      1. 6.4.1 Averaging and Conversion Time Considerations
      2. 6.4.2 Filtering and Input Considerations
    5. 6.5 Programming
      1. 6.5.1 Programming the Calibration Register
      2. 6.5.2 Programming the Power Measurement Engine
        1. 6.5.2.1 Calibration Register and Scaling
      3. 6.5.3 Simple Current Shunt Monitor Usage (No Programming Necessary)
      4. 6.5.4 Default Settings
      5. 6.5.5 Bus Overview
        1. 6.5.5.1 Serial Bus Address
        2. 6.5.5.2 Serial Interface
        3. 6.5.5.3 Writing to and Reading From the INA226-Q1
          1. 6.5.5.3.1 High-Speed I2C Mode
        4. 6.5.5.4 SMBus Alert Response
  8. 7 Registers
    1. 7.1 Register Maps
      1. 7.1.1  Configuration Register (00h) (Read/Write)
      2. 7.1.2  Shunt Voltage Register (01h) (Read-Only)
      3. 7.1.3  Bus Voltage Register (02h) (Read-Only) #GUID-792F23A7-1E45-4FB9-9334-0BF769622DE4/SBOS5477597
      4. 7.1.4  Power Register (03h) (Read-Only)
      5. 7.1.5  Current Register (04h) (Read-Only)
      6. 7.1.6  Calibration Register (05h) (Read/Write)
      7. 7.1.7  Mask/Enable Register (06h) (Read/Write)
      8. 7.1.8  Alert Limit Register (07h) (Read/Write)
      9. 7.1.9  Manufacturer ID Register (FEh) (Read-Only)
      10. 7.1.10 Die ID Register (FFh) (Read-Only)
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Applications
      1. 8.2.1 High-Side Sensing Circuit Application
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
        3. 8.2.1.3 Application Curves
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Device Support
      1. 9.1.1 Development Support
    2. 9.2 Receiving Notification of Documentation Updates
    3. 9.3 Support Resources
    4. 9.4 Trademarks
    5. 9.5 Electrostatic Discharge Caution
    6. 9.6 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

5.5 Electrical Characteristics

TA = 25°C, VVS = 3.3 V, VIN+ = 12 V, VSENSE = (VIN+ – VIN–) = 0 mV and VVBUS = 12 V, unless otherwise noted
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
INPUT
Shunt voltage input range –81.9175 81.92 mV
Bus voltage input range(1) 0 36 V
CMRR Common-mode rejection 0 V ≤ VIN+ ≤ 36 V 126 140 dB
VOS Shunt offset voltage, RTI(2) ±2.5 ±10 μV
Shunt offset voltage, RTI(2) vs temperature –40°C ≤ TA ≤ 125°C 0.02 0.1 μV/°C
PSRR Shunt offset voltage, RTI(2) vs Power supply 2.7 V ≤ VS ≤ 5.5 V ±2.5 μV/V
VOS Bus offset voltage, RTI(2) ±1.25 ±7.5 mV
Bus offset voltage, RTI(2) vs temperature –40°C ≤ TA ≤ 125°C 10 40 μV/°C
PSRR Bus offset voltage, RTI(2) vs power supply ±0.5 mV/V
IB Input bias current (IIN+, IIN– pins) 0.1 nA
VBUS input impedance 830 kΩ
Input leakage (3) (IN+ pin) + (IN– pin),
Power-down mode		 0.1 0.5 μA
DC ACCURACY
ADC native resolution 16 Bits
1 LSB step size Shunt voltage 2.5 μV
Bus voltage 1.25 mV
Shunt voltage gain error 0.02% 0.1%
Shunt voltage gain error vs temperature –40°C ≤ TA ≤ 125°C 10 50 ppm/°C
Bus voltage gain error 0.02% 0.1%
Bus voltage gain error vs temperature –40°C ≤ TA ≤ 125°C 10 50 ppm/°C
Differential nonlinearity ±0.1 LSB
tCT ADC conversion time CT bit = 000 140 154 μs
CT bit = 001 204 224
CT bit = 010 332 365
CT bit = 011 588 646
CT bit = 100 1.1 1.21 ms
CT bit = 101 2.116 2.328
CT bit = 110 4.156 4.572
CT bit = 111 8.244 9.068
SMBus
SMBus timeout(4) 28 35 ms
DIGITAL INPUT/OUTPUT
Input capacitance 3 pF
Leakage input current 0 V ≤ VSCL ≤ VVS ,
0 V ≤ VSDA ≤ VVS,
0 V ≤ VAlert ≤ VVS ,
0 V ≤ VA0 ≤ VVS ,
0 V ≤ VA1 ≤ VVS		 0.1 1 μA
VIH High-level input voltage 0.7×VVS 6 V
VIL Low-level input voltage –0.5 0.3×VVS V
VOL Low-level output voltage, SDA, Alert IOL = 3 mA 0 0.4 V
Hysteresis 500 mV
POWER SUPPLY
Operating supply range 2.7 5.5 V
IQ Quiescent current 330 420 μA
Quiescent current, power-down (shutdown) mode 0.5 2 μA
VPOR Power-on reset threshold 2 V
(1) While the input range is 36 V, the full-scale range of the ADC scaling is 40.96 V. See the Section 6.3.1. Do not apply more than 36 V.
(2) RTI = Referred-to-input.
(3) Input leakage is positive (current flowing into the pin) for the conditions shown at the top of this table. Negative leakage currents can occur under different input conditions.
(4) SMBus timeout in the device resets the interface any time SCL is low for more than 28 ms.