SLYS024A May 2020 – June 2021 INA229-Q1
PRODUCTION DATA
MIN | NOM | MAX | UNIT | ||
---|---|---|---|---|---|
SERIAL INTERFACE | |||||
fSPI | SPI bit frequency | 10 | MHz | ||
tSCLK_H | SCLK high time | 40 | ns | ||
tSCLK_L | SCLK low time | 40 | ns | ||
tCSF_SCLKR | CS fall to first SCLK rise time | 10 | ns | ||
tSCLKF_CSR | Last SCLK fall to CS rise time | 10 | ns | ||
tFRM_DLY | Sequential transfer delay (1) | 50 | ns | ||
tMOSI_RF | MOSI Rise and Fall time, 10 MHz SCLK | 15 | ns | ||
tMOSI_ST | MOSI data setup time | 10 | ns | ||
tMOSI_HLD | MOSI data hold time | 20 | ns | ||
tMISO_RF | MISO Rise and Fall time, CLOAD = 200 pF | 15 | ns | ||
tMISO_ST | MISO data setup time | 20 | ns | ||
tMISO_HLD | MISO data hold time | 20 | ns | ||
tCS_MISO_DLY | CS falling edge to MISO data valid delay time | 25 | ns | ||
tCS_MISO_HIZ | CS rising edge to MISO high impedance delay time | 25 | ns |