SBOS601A February   2012  – December 2021 INA230

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Related Products
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Timing Requirements (I2C)
    7. 7.7 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Basic ADC Functions
      2. 8.3.2 Power Calculation
      3. 8.3.3 Alert Pin
    4. 8.4 Device Functional Modes
      1. 8.4.1 Averaging and Conversion Time Considerations
      2. 8.4.2 Filtering and Input Considerations
    5. 8.5 Programming
      1. 8.5.1 Programming the Calibration Register
      2. 8.5.2 Programming the INA230 Power Measurement Engine
        1. 8.5.2.1 Calibration Register and Scaling
      3. 8.5.3 Simple Current Shunt Monitor Usage (No Programming Necessary)
      4. 8.5.4 Default INA230 Settings
      5. 8.5.5 Bus Overview
        1. 8.5.5.1 Serial Bus Address
        2. 8.5.5.2 Serial Interface
      6. 8.5.6 Writing to and Reading From the I2C Serial Interface
        1. 8.5.6.1 High-Speed I2C Mode
      7. 8.5.7 SMBus Alert Response
    6. 8.6 Register Maps
      1. 8.6.1 Configuration Register (00h, Read/Write)
      2. 8.6.2 AVG Bit Settings [11:9]
      3. 8.6.3 VBUS CT Bit Settings [8:6]
      4. 8.6.4 VSH CT Bit Settings [5:3]
      5. 8.6.5 Mode Settings [2:0]
      6. 8.6.6 Data Output Register
        1. 8.6.6.1 Shunt Voltage Register (01h, Read-Only)
        2. 8.6.6.2 Bus Voltage Register (02h, Read-Only) (1)
        3. 8.6.6.3 Power Register (03h, Read-Only)
        4. 8.6.6.4 Current Register (04h, Read-Only)
        5. 8.6.6.5 Calibration Register (05h, Read/Write)
        6. 8.6.6.6 Mask/Enable Register (06h, Read/Write)
        7. 8.6.6.7 Alert Limit Register (07h, Read/Write)
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Applications
      1. 9.2.1 High-Side Sensing Circuit Application
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
        3. 9.2.1.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Documentation Support
      1. 12.1.1 Related Documentation
    2. 12.2 Receiving Notification of Documentation Updates
    3. 12.3 Support Resources
    4. 12.4 Trademarks
    5. 12.5 Electrostatic Discharge Caution
    6. 12.6 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • RGT|16
  • DGS|10
Thermal pad, mechanical data (Package|Pins)
Orderable Information

8.5.5.2 Serial Interface

The INA230 operates only as a target device on both the I2C bus and the SMBus. Connections to the bus are made through the open-drain I/O lines, SDA, and SCL. The SDA and SCL pins feature integrated spike-suppression filters and Schmitt triggers to minimize the effects of input spikes and bus noise. Although there is spike suppression integrated into the digital I/O lines, proper layout should be used to minimize the amount of coupling into the communication lines. This noise introduction could occur from capacitively coupling signal edges between the two communication lines themselves or from other switching noise sources present in the system. Routing traces in parallel with ground in between layers on a printed circuit board (PCB) typically reduces the effects of coupling between the communication lines. Shielding communication lines in general is recommended to reduce to possibility of unintended noise coupling into the digital I/O lines that could be incorrectly interpreted as start or stop commands.

The INA230 supports the transmission protocol for Fast (1 kHz to 400 kHz) and High-speed (1 kHz to 3.4 MHz) modes. All data bytes are transmitted most significant byte first.