SBOS844C May   2021  – March 2023 INA234

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements (I2C)
    7. 6.7 Timing Diagram
    8. 6.8 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Integrated Analog-to-Digital Convertor (ADC)
      2. 7.3.2 Power Calculation
      3. 7.3.3 Low Bias Current
      4. 7.3.4 Low Voltage Supply and Wide Common-Mode Voltage Range
      5. 7.3.5 ALERT Pin
    4. 7.4 Device Functional Modes
      1. 7.4.1 Continuous Verses Triggered Operation
      2. 7.4.2 Device Shutdown
      3. 7.4.3 Power-On Reset
      4. 7.4.4 Averaging and Conversion Time Considerations
    5. 7.5 Programming
      1. 7.5.1 I2C Serial Interface
      2. 7.5.2 Writing to and Reading Through the I2C Serial Interface
      3. 7.5.3 High-Speed I2C Mode
      4. 7.5.4 General Call Reset
      5. 7.5.5 General Call Start Byte
      6. 7.5.6 SMBus Alert Response
    6. 7.6 Register Maps
      1. 7.6.1 Device Registers
  8. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Device Measurement Range and Resolution
      2. 8.1.2 Current and Power Calculations
      3. 8.1.3 ADC Output Data Rate and Noise Performance
      4. 8.1.4 Filtering and Input Considerations
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Select the Shunt Resistor
        2. 8.2.2.2 Configure the Device
        3. 8.2.2.3 Program the Shunt Calibration Register
        4. 8.2.2.4 Set Desired Fault Thresholds
        5. 8.2.2.5 Calculate Returned Values
      3. 8.2.3 Application Curves
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  9. 9 Device and Documentation Support
    1. 9.1 Device Support
      1. 9.1.1 Development Support
    2. 9.2 Documentation Support
      1. 9.2.1 Related Documentation
    3. 9.3 Receiving Notification of Documentation Updates
    4. 9.4 Support Resources
    5. 9.5 Trademarks
    6. 9.6 Electrostatic Discharge Caution
    7. 9.7 Glossary
  10. 10Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • YBJ|8
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7.6.1 Device Registers

Table 7-2 lists the INA234 registers. All register locations not listed in Table 7-2 should be considered as reserved locations and the register contents should not be modified.

Table 7-2 INA234 Registers
AddressRegister NameRegister Size (bits)Reset ValueSection
0hConfiguration Register164127hGo
1hShunt Voltage Register160000hGo
2hBus Voltage Register160000hGo
3hPower Register160000hGo
4hCurrent Register160000hGo
5hCalibration Register160000hGo
6hMask/Enable Register160000hGo
7hAlert Limit Register160000hGo
3EhManufacturer ID Register165449hGo
3Fh Device ID Register 16 A480h Go

Complex bit access types are encoded to fit into small table cells. Table 7-3 shows the codes that are used for access types in this section.

Table 7-3 Device Access Type Codes
Access TypeCodeDescription
Read Type
RRRead
Write Type
WWWrite

7.6.1.1 Configuration Register (Address = 0h) [reset = 4127h]

The configuration register is shown in Table 7-4.

Table 7-4 Configuration Register Field Descriptions
BitFieldTypeResetDescription
15RSTR/W0bSet this bit to '1' to generate a system reset that is the same as power-on reset.
Resets all registers to default values and then self-clears.

0b = Normal Operation

1b = System Reset self clears registers to default values

14-13ReservedR10bReserved value always returns 10b
12ADCRANGER/W0bEnables the selection of the shunt full scale input across IN+ and IN–.

0b = ±81.92 mV

1b = ±20.48 mV

11-9AVGR/W000bSets the number of ADC conversion results to be averaged. The read-back registers are updated after averaging is completed.

000b = 1

001b = 4

010b = 16

011b = 64

100b = 128

101b = 256

110b = 512

111b = 1024

8-6VBUSCTR/W100bSets the conversion time of the VBUS measurement

000b = 140 µs

001b = 204 µs

010b = 332 µs

011b = 588 µs

100b = 1100 µs

101b = 2116 µs

110b = 4156 µs

111b = 8244 µs

5-3VSHCTR/W

100b

Sets the conversion time of the SHUNT measurement

000b = 140 µs

001b = 204 µs

010b = 332 µs

011b = 588 µs

100b = 1100 µs

101b = 2116 µs

110b = 4156 µs

111b = 8244 µs

2-0MODER/W

111b

Operating mode, modes can be selected to operate the device either in Shutdown mode, continuous mode or triggered mode.
The mode also allows user to select mux settings to set continuous or triggered mode on bus voltage, shunt voltage measurement.

000b = Shutdown

001b = Shunt Voltage triggered, single shot

010b = Bus Voltage triggered, single shot

011b = Shunt voltage and Bus voltage triggered, single shot

100b = Shutdown

101b = Continuous Shunt voltage

110b = Continuous Bus voltage

111b = Continuous Shunt and Bus voltage

Return to the Summary Table.

7.6.1.2 Shunt Voltage Register (Address = 1h) [reset = 0000h]

The Shunt Voltage Register stores the current shunt voltage reading, VSHUNT and is show in Table 7-5. Negative numbers are represented in two's complement format. Generate the two's complement of a negative number by complementing the absolute value binary number and adding 1. An MSB = '1' denotes a negative number.

Example: For a value of VSHUNT = –80 mV:

  1. Take the absolute value: 80 mV
  2. Translate this number to a whole decimal number (80 mV ÷ 2.5 µV) = 32000
  3. Convert this number to binary = 0111 1101 0000 0000
  4. Complement the binary result = 1000 0010 1111 1111
  5. Add '1' to the complement to create the two's complement result = 1000 0011 0000 0000 = 8300h

If averaging is enabled, this register displays the averaged value.

Table 7-5 Shunt Voltage Register Field Descriptions
BitFieldTypeResetDescription
15-4VSHUNTR000hDifferential voltage measured across the shunt output. Two's complement value.
3-0ReservedR0hAlways returns 0. Remove these bits from the full result by doing a right arithmetic shift
Return to the Summary Table.

7.6.1.3 Bus Voltage Register (Address = 2h) [reset = 0000h]

The bus voltage register is shown in Table 7-6.

This register will only return positive values. If averaging is enabled, this register displays the averaged value.

Table 7-6 Bus Voltage Register Field Descriptions
BitFieldTypeResetDescription
15ReservedR0bThis bit returns Zero as common mode voltage is only positive
14-4VBUSR000hThese bits readout the bus voltage of the system
3-0ReservedR0hAlways returns 0. Remove these bits from the full result by doing a right arithmetic shift
Return to the Summary Table.

7.6.1.4 POWER Register (Address = 3h) [reset = 0000h]

The power register is shown in Table 7-7.

If averaging is enabled, this register displays the averaged value. The Power Register records power in Watts by multiplying the decimal values of the Current Register with the decimal value of the Bus Voltage Register. This is an unsigned result.

Table 7-7 POWER Register Field Descriptions
BitFieldTypeResetDescription
15-0POWERR0000hThis bit returns a calculated value of power in the system.
This is an unsigned result.
Return to the Summary Table.

7.6.1.5 CURRENT Register (Address = 4h) [reset = 0000h]

CURRENT is shown in Table 7-8.

If averaging is enabled, this register displays the averaged value. The value of the Current Register is calculated by multiplying the decimal value in the Shunt Voltage Register with the decimal value of the Calibration Register.

Table 7-8 CURRENT Register Field Descriptions
BitFieldTypeResetDescription
15-4CURRENTR000hCalculated current output in Amperes. Two's complement value.
3-0RESERVEDR0hAlways returns 0. Remove these bits from the full result by doing a right arithmetic shift
Return to the Summary Table.

7.6.1.6 Calibration Register (Address = 5h) [reset = 0000h]

The calibration register shown in Table 7-9 must be programmed to receive valid current and power results after initial power up or power cycle events.

This register provides the device with the value of the shunt resistor that was present to create the measured differential voltage. It also sets the resolution of the Current Register. Programming this register sets the Current_LSB and the Power_LSB.

Table 7-9 Calibration Register Field Descriptions
BitFieldTypeResetDescription
15ReservedR0h
14-0SHUNT_CALR/W0000hProgrammed value needed for doing the shunt voltage to current conversion.
Return to the Summary Table.

7.6.1.7 Mask/Enable Register (Address = 6h) [reset = 0000h]

The Mask/Enable Register is shown in Table 7-10.

Table 7-10 Mask/Enable Register Field Descriptions
BitFieldTypeResetDescription
15SOL (Shunt Over-limit)R/W0b

Setting this bit high configures the ALERT pin to be asserted if the shunt voltage conversion result exceeds the value programmed in the LIMIT register

14SUL (Shunt Under-limit)R/W0b

Setting this bit high configures the ALERT pin to be asserted if the shunt voltage conversion result is below the value programmed in the LIMIT register.

Cannot be set if Shunt overlimit is set.

13BOL (Bus Over-limit)R/W0b

Setting this bit high configures the ALERT pin to be asserted if the bus voltage conversion result exceeds the value programmed in the LIMIT register

Cannot be set if Shunt overlimit or Shunt underlimit is set.

12BUL (Bus Under-limit)R/W0b

Setting this bit high configures the ALERT pin to be asserted if the bus voltage conversion result is below the value programmed in the LIMIT register

Cannot be set if Shunt over limit, Shunt under limit or Bus over limit is set.

11POL (Power Over-limit)R/W0b

Setting this bit high configures the ALERT pin to be asserted if the power result exceeds the value programmed in the LIMIT register

Cannot be set if Shunt over limit, Shunt under limit, Bus over limit or Bus under limit is set.

10CNVR (Conversion Ready)R/W0b

Setting this bit high configures the ALERT pin to be asserted when the Conversion Ready Flag, Bit 3, is asserted indicating that the device is ready for the next conversion.

0b = Disable conversion ready flag on ALERT pin

1b = Enables conversion ready flag on ALERT pin

9-6ReservedR0000b
5MemErrorR0bCRC or ECC error
4AFF (Alert Function Flag)R0b

Alert Function Flag -While only one Alert Function can be monitored at the ALERT pin at a time, the Conversion Ready can also be enabled to assert the ALERT pin. Reading the Alert Function Flag following an alert allows the user to determine if the Alert Function was the source of the Alert.

When the Alert Latch Enable bit is set to Latch mode, the Alert Function Flag bit clears only when the Mask/Enable Register is read. When the Alert Latch Enable bit is set to Transparent mode, the Alert Function Flag bit is cleared following the next conversion that does not result in an Alert condition.

3CVRF (Conversion Ready Flag)R0b

Although the device can be read at any time, and the data from the last conversion is available, the Conversion Ready Flag bit is provided to help coordinate one-shot or triggered conversions.

The Conversion Ready Flag bit is set after all conversions, averaging, and multiplications are complete.

Conversion Ready Flag bit clears under the following conditions:

1.) Writing to the Configuration Register (except for Power-Down selection)

2.) Reading the Mask/Enable Register

2OVF (Math Over-flow)R0bThis bit is set to '1' if an arithmetic operation resulted in an overflow error. It indicates that current and power data may be invalid.
1APOL (Alert Polarity)R/W0b

Alert Polarity bit sets the Alert pin polarity.

0b = Normal (Active-low open drain)

1b= Inverted (active-high )

0LEN (Alert Latch Enable)R/W0b

When the Alert Latch Enable bit is set to Transparent mode, the Alert pin and Alert Function Flag (AFF) bit resets to the idle states when the fault condition has been cleared.

When the Alert Latch Enable bit is set to Latch mode, the Alert pin and AFF bit remains active following a fault until this register flag has been read.

This bit must be set to use the I2C Alert Response function.

0b = Transparent

1b = Latched Alert pin

Return to the Summary Table.

7.6.1.8 Alert Limit Register (Address = 7h) [reset = 0000h]

The alert limit register is shown in Table 7-11.

Table 7-11 Alert Limit Register Field Descriptions
BitFieldTypeResetDescription
15-0LIMITR/W0000h

The Alert Limit Register contains the value used to compare to the register selected in the Mask/Enable Register to determine if a limit has been exceeded.

A two's complement value must be used for the Shunt Over Voltage limit. Limit values entered should match the format of the targeted register
Return to the Summary Table.

7.6.1.9 Manufacturer ID Register (Address = 3Eh) [reset = 5449h]

The manufacturer ID register is shown in Table 7-12.

Table 7-12 MANUFACTURE_ID Register Field Descriptions
BitFieldTypeResetDescription
15-0MANUFACTURE_IDR5449hReads back TI in ASCII
Return to the Summary Table.

7.6.1.10 Device ID Register (Address = 3Fh) [reset = A480h]

The Device ID register is shown in Table 7-13.

Table 7-13 DEVICE_ID Register Field Descriptions
Bit Field Type Reset Description
15-3 DIEID R A480h Stores the device identification bits
3-0 Reserved R 0h Always read 0
Return to the Summary Table.