SBOS844C May   2021  – March 2023 INA234

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements (I2C)
    7. 6.7 Timing Diagram
    8. 6.8 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Integrated Analog-to-Digital Convertor (ADC)
      2. 7.3.2 Power Calculation
      3. 7.3.3 Low Bias Current
      4. 7.3.4 Low Voltage Supply and Wide Common-Mode Voltage Range
      5. 7.3.5 ALERT Pin
    4. 7.4 Device Functional Modes
      1. 7.4.1 Continuous Verses Triggered Operation
      2. 7.4.2 Device Shutdown
      3. 7.4.3 Power-On Reset
      4. 7.4.4 Averaging and Conversion Time Considerations
    5. 7.5 Programming
      1. 7.5.1 I2C Serial Interface
      2. 7.5.2 Writing to and Reading Through the I2C Serial Interface
      3. 7.5.3 High-Speed I2C Mode
      4. 7.5.4 General Call Reset
      5. 7.5.5 General Call Start Byte
      6. 7.5.6 SMBus Alert Response
    6. 7.6 Register Maps
      1. 7.6.1 Device Registers
  8. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Device Measurement Range and Resolution
      2. 8.1.2 Current and Power Calculations
      3. 8.1.3 ADC Output Data Rate and Noise Performance
      4. 8.1.4 Filtering and Input Considerations
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Select the Shunt Resistor
        2. 8.2.2.2 Configure the Device
        3. 8.2.2.3 Program the Shunt Calibration Register
        4. 8.2.2.4 Set Desired Fault Thresholds
        5. 8.2.2.5 Calculate Returned Values
      3. 8.2.3 Application Curves
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  9. 9 Device and Documentation Support
    1. 9.1 Device Support
      1. 9.1.1 Development Support
    2. 9.2 Documentation Support
      1. 9.2.1 Related Documentation
    3. 9.3 Receiving Notification of Documentation Updates
    4. 9.4 Support Resources
    5. 9.5 Trademarks
    6. 9.6 Electrostatic Discharge Caution
    7. 9.7 Glossary
  10. 10Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • YBJ|8
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6.5 Electrical Characteristics

at TA = 25°C, VS = 3.3 V, VSENSE = VIN+ - VIN– = 0 mV, VIN– = VBUS = 12 V (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
INPUT
CMRR Common-mode rejection VCM = –0.3 V to 28 V, TA = –40°C to 125°C 100 120 dB
Shunt voltage input range ADCRANGE = 0 –81.9175 81.92 mV
ADCRANGE = 1 –20.4794 20.48 mV
Vos Shunt offset voltage VCM = 12 V ±100 µV
dVos/dT Shunt offset voltage drift TA = –40°C to +125°C ±0.5 µV/°C
Vos_b IN- bus offset Voltage ±15 mV
dVos_b/dT IN- bus offset voltage drift TA = –40°C to +125°C ±100 µV/°C
PSRRSHUNT Power supply rejection ratio
(Current measurements)		 VS = 1.7 V to 5.5 V, TA = –40°C to 125°C ±0.5 ±2.5 µV/V
PSRRBUS Power supply rejection ratio
(Voltage measurements)		 VS = 1.7 V to 5.5 V, TA = –40°C to 125°C, VIN– = 105 mV ±0.5 ±2.5 mV/V
ZIN- IN- input impedance Bus Voltage Measurement Mode 1.05 MΩ
IB_SHDWN Input Leakage IN+, IN–, Shutdown Mode 0.1 5 nA
IB Input bias current IN+, IN–, Current Measurement Mode 0.1 10 nA
DC ACCURACY
RDIFF Differential Input Impedance
(IN+ to IN-)		 Shunt or Current Measurement Modes, VIN+ – VIN– < 82 mV  140 kΩ
ADC Resolution TA = –40°C to 125°C 12 Bits
1 LSB step size Shunt Voltage, ADCRANGE = 0 40 µV
Shunt Voltage, ADCRANGE = 1 10 µV
Bus Voltage 25.6 mV
ADC Conversion-time
(TA = –40°C to 125°C)		 CT bit = 000 133 140 147 µs
CT bit = 001 194 204 214 µs
CT bit = 010 315 332 349 µs
CT bit = 011 559 588 617 µs
CT bit = 100 1.045 1.100 1.155 ms
CT bit = 101 2.01 2.116 2.222 ms
CT bit = 110 3.948 4.156 4.364 ms
CT bit = 111 7.832 8.244 8.656 ms
GSERR Shunt voltage gain error ±0.5 %
GS_DRFT Shunt voltage gain error drift TA = –40°C to +125°C 50 ppm/°C
GBERR VIN- voltage gain error ±0.5 %
GB_DRFT VIN- voltage gain error drift TA = –40°C to +125°C 50 ppm/°C
INL Integral Non-Linearity ±2 m%
DNL Differential Non-Linearity ±0.1 LSB
POWER SUPPLY
IQ Quiescent current VSENSE = 0 mV 300 380 µA
IQ vs temperature, TA = –40°C to +125°C 500 µA
Shutdown 2.2 3 µA
VPOR Power-on reset threshold VS falling 0.95 V
SMBUS
SMBUS timeout 28 35 ms
DIGITAL INPUT / OUTPUT
Input capacitance 3 pF
VIH Logic input level, high VS = 1.7 V to 5.5 V, TA = –40°C to +125°C 0.9 5.5 V
VIL Logic input level, low VS = 1.7 V to 5.5 V, TA = –40°C to +125°C 0 0.4 V
VHYS Hysteresis 130 mV
VOL Logic output level, low IOL = 3 mA, VS = 1.7 V to 5.5 V, TA = –40°C to +125°C 0 0.3 V
Digital leakage input current 0 ≤ VINPUT ≤ VS  –1 1 µA