SLYS025A January   2021  – May 2022 INA238

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements (I2C)
    7. 6.7 Timing Diagram
    8. 6.8 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Versatile High Voltage Measurement Capability
      2. 7.3.2 Power Calculation
      3. 7.3.3 Low Bias Current
      4. 7.3.4 High-Precision Delta-Sigma ADC
        1. 7.3.4.1 Low Latency Digital Filter
        2. 7.3.4.2 Flexible Conversion Times and Averaging
      5. 7.3.5 Integrated Precision Oscillator
      6. 7.3.6 Multi-Alert Monitoring and Fault Detection
    4. 7.4 Device Functional Modes
      1. 7.4.1 Shutdown Mode
      2. 7.4.2 Power-On Reset
    5. 7.5 Programming
      1. 7.5.1 I2C Serial Interface
        1. 7.5.1.1 Writing to and Reading Through the I2C Serial Interface
        2. 7.5.1.2 High-Speed I2C Mode
        3. 7.5.1.3 SMBus Alert Response
    6. 7.6 Register Maps
      1. 7.6.1 INA238 Registers
  8. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Device Measurement Range and Resolution
      2. 8.1.2 Current and Power Calculations
      3. 8.1.3 ADC Output Data Rate and Noise Performance
      4. 8.1.4 Input Filtering Considerations
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Select the Shunt Resistor
        2. 8.2.2.2 Configure the Device
        3. 8.2.2.3 Program the Shunt Calibration Register
        4. 8.2.2.4 Set Desired Fault Thresholds
        5. 8.2.2.5 Calculate Returned Values
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Receiving Notification of Documentation Updates
    2. 11.2 Support Resources
    3. 11.3 Trademarks
    4. 11.4 Electrostatic Discharge Caution
    5. 11.5 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7.6.1 INA238 Registers

Table 7-3 lists the INA238 registers. All register locations not listed in Table 7-3 should be considered as reserved locations and the register contents should not be modified.

Table 7-3 INA238 Registers

Address

 Acronym Register Name Register Size (bits) Section
0h CONFIG Configuration 16 Go
1h ADC_CONFIG ADC Configuration 16 Go
2h SHUNT_CAL Shunt Calibration 16 Go
4h VSHUNT Shunt Voltage Measurement 16 Go
5h VBUS Bus Voltage Measurement 16 Go
6h DIETEMP Temperature Measurement 16 Go
7h CURRENT Current Result 16 Go
8h POWER Power Result 24 Go
Bh DIAG_ALRT Diagnostic Flags and Alert 16 Go
Ch SOVL Shunt Overvoltage Threshold 16 Go
Dh SUVL Shunt Undervoltage Threshold 16 Go
Eh BOVL Bus Overvoltage Threshold 16 Go
Fh BUVL Bus Undervoltage Threshold 16 Go
10h TEMP_LIMIT Temperature Over-Limit Threshold 16 Go
11h PWR_LIMIT Power Over-Limit Threshold 16 Go
3Eh MANUFACTURER_ID Manufacturer ID 16 Go
3Fh DEVICE_ID Device ID 16 Go

Complex bit access types are encoded to fit into small table cells. Table 7-4 shows the codes that are used for access types in this section.

Table 7-4 INA238 Access Type Codes
Access Type Code Description
Read Type
R R Read
Write Type
W W Write
Reset or Default Value
-n Value after reset or the default value

7.6.1.1 Configuration (CONFIG) Register (Address = 0h) [reset = 0h]

The CONFIG register is shown in Table 7-5.

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Table 7-5 CONFIG Register Field Descriptions
Bit Field Type Reset Description
15 RST R/W 0h Reset Bit. Setting this bit to '1' generates a system reset that is the same as power-on reset.
Resets all registers to default values.

0h = Normal Operation

1h = System Reset sets registers to default values


This bit self-clears.
14 RESERVED R/W 0h Reserved. Always reads 0.
13-6 CONVDLY R/W 0h Sets the Delay for initial ADC conversion in steps of 2 ms.

0h = 0 s

1h = 2 ms

FFh = 510 ms
5 RESERVED R/W 0h Reserved. Always reads 0.
4 ADCRANGE R/W 0h Shunt full scale range selection across IN+ and IN–.

0h = ±163.84 mV

1h = ± 40.96 mV
3-0 RESERVED R 0h Reserved. Always reads 0.

7.6.1.2 ADC Configuration (ADC_CONFIG) Register (Address = 1h) [reset = FB68h]

The ADC_CONFIG register is shown in Table 7-6.

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Table 7-6 ADC_CONFIG Register Field Descriptions
Bit Field Type Reset Description
15-12 MODE R/W Fh The user can set the MODE bits for continuous or triggered mode on bus voltage, shunt voltage or temperature measurement.

0h = Shutdown

1h = Triggered bus voltage, single shot

2h = Triggered shunt voltage, single shot

3h = Triggered shunt voltage and bus voltage, single shot

4h = Triggered temperature, single shot

5h = Triggered temperature and bus voltage, single shot

6h = Triggered temperature and shunt voltage, single shot

7h = Triggered bus voltage, shunt voltage and temperature, single shot

8h = Shutdown

9h = Continuous bus voltage only

Ah = Continuous shunt voltage only

Bh = Continuous shunt and bus voltage

Ch = Continuous temperature only

Dh = Continuous bus voltage and temperature

Eh = Continuous temperature and shunt voltage

Fh = Continuous bus voltage, shunt voltage and temperature
11-9 VBUSCT R/W 5h Sets the conversion time of the bus voltage measurement:

0h = 50 µs

1h = 84 µs

2h = 150 µs

3h = 280 µs

4h = 540 µs

5h = 1052 µs

6h = 2074 µs

7h = 4120 µs
8-6 VSHCT R/W 5h Sets the conversion time of the shunt voltage measurement:

0h = 50 µs

1h = 84 µs

2h = 150 µs

3h = 280 µs

4h = 540 µs

5h = 1052 µs

6h = 2074 µs

7h = 4120 µs
5-3 VTCT R/W 5h Sets the conversion time of the temperature measurement:

0h = 50 µs

1h = 84 µs

2h = 150 µs

3h = 280 µs

4h = 540 µs

5h = 1052 µs

6h = 2074 µs

7h = 4120 µs
2-0 AVG R/W 0h Selects ADC sample averaging count. The averaging setting applies to all active inputs.
When >0h, the output registers are updated after the averaging has completed.

0h = 1

1h = 4

2h = 16

3h = 64

4h = 128

5h = 256

6h = 512

7h = 1024

7.6.1.3 Shunt Calibration (SHUNT_CAL) Register (Address = 2h) [reset = 1000h]

The SHUNT_CAL register is shown in Table 7-7.

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Table 7-7 SHUNT_CAL Register Field Descriptions
Bit Field Type Reset Description
15 RESERVED R 0h Reserved. Always reads 0.
14-0 SHUNT_CAL R/W 1000h The register provides the device with a conversion constant value that represents shunt resistance used to calculate current value in Amperes.
This also sets the resolution for the CURRENT register.
Value calculation under Section 8.1.2.

7.6.1.4 Shunt Voltage Measurement (VSHUNT) Register (Address = 4h) [reset = 0h]

The VSHUNT register is shown in Table 7-8.

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Table 7-8 VSHUNT Register Field Descriptions
Bit Field Type Reset Description
15-0 VSHUNT R 0h Differential voltage measured across the shunt output. Two's complement value.
Conversion factor:
5 µV/LSB when ADCRANGE = 0
1.25 µV/LSB when ADCRANGE = 1

7.6.1.5 Bus Voltage Measurement (VBUS) Register (Address = 5h) [reset = 0h]

The VBUS register is shown in Table 7-9.

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Table 7-9 VBUS Register Field Descriptions
Bit Field Type Reset Description
15-0 VBUS R 0h Bus voltage output. Two's complement value, however always positive.
Conversion factor: 3.125 mV/LSB

7.6.1.6 Temperature Measurement (DIETEMP) Register (Address = 6h) [reset = 0h]

The DIETEMP register is shown in Table 7-10.

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Table 7-10 DIETEMP Register Field Descriptions
Bit Field Type Reset Description
15-4 DIETEMP R 0h Internal die temperature measurement. Two's complement value.
Conversion factor: 125 m°C/LSB
3-0 RESERVED R 0h Reserved. Always reads 0.

7.6.1.7 Current Result (CURRENT) Register (Address = 7h) [reset = 0h]

The CURRENT register is shown in Table 7-11.

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Table 7-11 CURRENT Register Field Descriptions
Bit Field Type Reset Description
15-0 CURRENT R 0h Calculated current output in Amperes. Two's complement value.
Value description under Section 8.1.2.

7.6.1.8 Power Result (POWER) Register (Address = 8h) [reset = 0h]

The POWER register is shown in Table 7-12.

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Table 7-12 POWER Register Field Descriptions
Bit Field Type Reset Description
23-0 POWER R 0h Calculated power output.
Output value in watts.
Unsigned representation. Positive value.
Value description under Section 8.1.2.

7.6.1.9 Diagnostic Flags and Alert (DIAG_ALRT) Register (Address = Bh) [reset = 0001h]

The DIAG_ALRT register is shown in Table 7-13.

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Table 7-13 DIAG_ALRT Register Field Descriptions
Bit Field Type Reset Description
15 ALATCH R/W 0h When the Alert Latch Enable bit is set to Transparent mode, the Alert pin and Flag bit reset to the idle state when the fault has been cleared.
When the Alert Latch Enable bit is set to Latch mode, the Alert pin and Alert Flag bit remain active following a fault until the DIAG_ALRT Register has been read.

0h = Transparent

1h = Latched
14 CNVR R/W 0h Setting this bit high configures the Alert pin to be asserted when the Conversion Ready Flag (bit 1) is asserted, indicating that a conversion cycle has completed.

0h = Disable conversion ready flag on ALERT pin

1h = Enables conversion ready flag on ALERT pin
13 SLOWALERT R/W 0h When enabled, ALERT function is asserted on the completed averaged value.
This gives the flexibility to delay the ALERT until after the averaged value.

0h = ALERT comparison on non-averaged (ADC) value

1h = ALERT comparison on averaged value
12 APOL R/W 0h Alert Polarity bit sets the Alert pin polarity.

0h = Normal (Active-low, open-drain)

1h = Inverted (active-high, open-drain )
11-10 RESERVED R 0h Reserved. Always read 0.
9 MATHOF R 0h This bit is set to 1 if an arithmetic operation resulted in an overflow error.
It indicates that current and power data may be invalid.

0h = Normal

1h = Overflow

Must be manually cleared by triggering another conversion.
8 RESERVED R 0h Reserved. Always read 0.
7 TMPOL R/W 0h This bit is set to 1 if the temperature measurement exceeds the threshold limit in the temperature over-limit register.

0h = Normal

1h = Over Temp Event


When ALATCH =1 this bit is cleared by reading this register.
6 SHNTOL R/W 0h This bit is set to 1 if the shunt voltage measurement exceeds the threshold limit in the shunt over-limit register.

0h = Normal

1h = Over Shunt Voltage Event


When ALATCH =1 this bit is cleared by reading this register.
5 SHNTUL R/W 0h This bit is set to 1 if the shunt voltage measurement falls below the threshold limit in the shunt under-limit register.

0h = Normal

1h = Under Shunt Voltage Event


When ALATCH =1 this bit is cleared by reading this register.
4 BUSOL R/W 0h This bit is set to 1 if the bus voltage measurement exceeds the threshold limit in the bus over-limit register.

0h = Normal

1h = Bus Over-Limit Event


When ALATCH =1 this bit is cleared by reading this register.
3 BUSUL R/W 0h This bit is set to 1 if the bus voltage measurement falls below the threshold limit in the bus under-limit register.

0h = Normal

1h = Bus Under-Limit Event


When ALATCH =1 this bit is cleared by reading this register.
2 POL R/W 0h This bit is set to 1 if the power measurement exceeds the threshold limit in the power limit register.

0h = Normal

1h = Power Over-Limit Event


When ALATCH =1 this bit is cleared by reading this register.
1 CNVRF R/W 0h This bit is set to 1 if the conversion is completed.

0h = Normal

1h = Conversion is complete


When ALATCH =1 this bit is cleared by reading this register or starting a new triggered conversion.
0 MEMSTAT R/W 1h This bit is set to 0 if a checksum error is detected in the device trim memory space.

0h = Memory Checksum Error

1h = Normal Operation

7.6.1.10 Shunt Overvoltage Threshold (SOVL) Register (Address = Ch) [reset = 7FFFh]

If negative values are entered in this register, then a shunt voltage measurement of 0 V will trip this alarm. When using negative values for the shunt under and overvoltage thresholds be aware that the over voltage threshold must be set to the larger (that is, less negative) of the two values. The SOVL register is shown in Table 7-14.

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Table 7-14 SOVL Register Field Descriptions
Bit Field Type Reset Description
15-0 SOVL R/W 7FFFh Sets the threshold for comparison of the value to detect Shunt Overvoltage (overcurrent protection). Two's complement value. Conversion Factor: 5 µV/LSB when ADCRANGE = 0
1.25 µV/LSB when ADCRANGE = 1.

7.6.1.11 Shunt Undervoltage Threshold (SUVL) Register (Address = Dh) [reset = 8000h]

The SUVL register is shown in Table 7-15.

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Table 7-15 SUVL Register Field Descriptions
Bit Field Type Reset Description
15-0 SUVL R/W 8000h Sets the threshold for comparison of the value to detect Shunt Undervoltage (undercurrent protection). Two's complement value. Conversion Factor: 5 µV/LSB when ADCRANGE = 0
1.25 µV/LSB when ADCRANGE = 1.

7.6.1.12 Bus Overvoltage Threshold (BOVL) Register (Address = Eh) [reset = 7FFFh]

The BOVL register is shown in Table 7-16.

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Table 7-16 BOVL Register Field Descriptions
Bit Field Type Reset Description
15 Reserved R 0h Reserved. Always reads 0.
14-0 BOVL R/W 7FFFh Sets the threshold for comparison of the value to detect Bus Overvoltage (overvoltage protection). Unsigned representation, positive value only. Conversion factor: 3.125 mV/LSB.

7.6.1.13 Bus Undervoltage Threshold (BUVL) Register (Address = Fh) [reset = 0h]

The BUVL register is shown in Table 7-17.

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Table 7-17 BUVL Register Field Descriptions
Bit Field Type Reset Description
15 Reserved R 0h Reserved. Always reads 0.
14-0 BUVL R/W 0h Sets the threshold for comparison of the value to detect Bus Undervoltage (undervoltage protection). Unsigned representation, positive value only. Conversion factor: 3.125 mV/LSB.

7.6.1.14 Temperature Over-Limit Threshold (TEMP_LIMIT) Register (Address = 10h) [reset = 7FFFh]

The TEMP_LIMIT register is shown in Table 7-18.

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Table 7-18 TEMP_LIMIT Register Field Descriptions
Bit Field Type Reset Description
15-4 TOL R/W 7FFh Sets the threshold for comparison of the value to detect over temperature measurements. Two's complement value.
The value entered in this field compares directly against the value from the DIETEMP register to determine if an over temperature condition exists. Conversion factor: 125 m°C/LSB.
3-0 Reserved R 0 Reserved, always reads 0

7.6.1.15 Power Over-Limit Threshold (PWR_LIMIT) Register (Address = 11h) [reset = FFFFh]

The PWR_LIMIT register is shown in Table 7-19.

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Table 7-19 PWR_LIMIT Register Field Descriptions
Bit Field Type Reset Description
15-0 POL R/W FFFFh Sets the threshold for comparison of the value to detect power over-limit measurements. Unsigned representation, positive value only.
The value entered in this field compares directly against the value from the POWER register to determine if an over power condition exists. Conversion factor: 256 × Power LSB.

7.6.1.16 Manufacturer ID (MANUFACTURER_ID) Register (Address = 3Eh) [reset = 5449h]

The MANUFACTURER_ID register is shown in Table 7-20.

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Table 7-20 MANUFACTURER_ID Register Field Descriptions
Bit Field Type Reset Description
15-0 MANFID R 5449h Reads back TI in ASCII.

7.6.1.17 Device ID (DEVICE_ID) Register (Address = 3Fh) [reset = 2381h]

The DEVICE_ID register is shown in Table 7-21.

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Table 7-21 DEVICE_ID Register Field Descriptions
Bit Field Type Reset Description
15-4 DIEID R 238h Stores the device identification bits.
3-0 REV_ID R 1h Device revision identification.