SBOS656C July   2016  – December 2016 INA260

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Related Products
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Integrated Shunt Resistor
      2. 8.3.2 Over-Current Capability
      3. 8.3.3 Basic ADC Functions
        1. 8.3.3.1 Power Calculation
        2. 8.3.3.2 ALERT Pin
    4. 8.4 Device Functional Modes
      1. 8.4.1 Averaging and Conversion Time Considerations
    5. 8.5 Programming
      1. 8.5.1 Calculating Returned Values
      2. 8.5.2 Default Settings
      3. 8.5.3 Communications Bus Overview
        1. 8.5.3.1 Serial Bus Address
        2. 8.5.3.2 Serial Interface
        3. 8.5.3.3 Writing to and Reading From the INA260
          1. 8.5.3.3.1 High-Speed I2C Mode
        4. 8.5.3.4 SMBus Alert Response
    6. 8.6 Register Maps
      1. 8.6.1 Configuration Register (00h) (Read/Write)
      2. 8.6.2 Current Register (01h) (Read-Only)
      3. 8.6.3 Bus Voltage Register (02h) (Read-Only)
      4. 8.6.4 Power Register (03h) (Read-Only)
      5. 8.6.5 Mask/Enable Register (06h) (Read/Write)
      6. 8.6.6 Alert Limit Register (07h) (Read/Write)
      7. 8.6.7 Manufacturer ID Register (FEh) (Read-Only)
      8. 8.6.8 Die ID Register (FFh) (Read-Only)
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Device Support
      1. 12.1.1 Third-Party Products Disclaimer
    2. 12.2 Documentation Support
      1. 12.2.1 Related Documentation
    3. 12.3 Receiving Notification of Documentation Updates
    4. 12.4 Community Resources
    5. 12.5 Trademarks
    6. 12.6 Electrostatic Discharge Caution
    7. 12.7 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

9 Application and Implementation

NOTE

Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Validate and test the design implementation to confirm system functionality.

9.1 Application Information

The INA260 is a current shunt and power monitor with an I2C-compatible interface. The device monitors both a shunt current and bus supply voltage. The internally calibrated integrated current sense resistor combined with an internal multiplier, enable direct readouts of current in amperes and power in watts.

9.2 Typical Application

INA260 p1_fbd_sbos656.gif Figure 30. Typical Circuit Configuration, INA260

9.2.1 Design Requirements

The INA260 measures current and the bus supply voltage and calculates power. It comes with alert capability where the ALERT pin can be programmed to respond to a user-defined event or to a conversion ready notification. This design illustrates the ability of the ALERT pin to respond to a set threshold.

9.2.2 Detailed Design Procedure

The ALERT pin can be configured to respond to one of the five alert functions described in the ALERT Pin section. The ALERT pin must be pulled up to the VS pin voltage through an external pullup resistor. The configuration register is set based on the required conversion time and averaging. The Mask/Enable Register is set to identify the required alert function and the Alert Limit Register is set to the limit value used for comparison.

9.2.3 Application Curves

Figure 32 shows the ALERT pin response to a bus over voltage limit of 5.5 V for a conversion time (tCT) of 1.1 ms and averaging set to 1. Figure 31 shows the response for the same limit but with the conversion time reduced to 140 µs. For the scope shots shown in these figures, persistence was enabled on the ALERT channel. This shows how the ALERT response time can vary depending on when the fault condition occurs relative to the internal ADC clock of the INA260. For fault conditions that are just exceeding the limit threshold the response time for the ALERT pin can vary from 1 to 2 conversion cycles. As mentioned, the variation is due to the timing on when the fault event occurs relative to the start time of the internal ADC conversion cycle. For fault events that greatly exceed the limit threshold it is possible for the alert to respond in less than one conversion cycle. This is because it takes fewer samples for the average to exceed the limit threshold value.

INA260 app_140us_SBOS656.gif
See Table 17 tCT = 140 µs
See Table 19 See Table 20
Figure 31. Alert Response
INA260 app_1p1ms_SBOS656.gif
See Table 18 tCT = 1.1 ms
See Table 19 See Table 20
Figure 32. Alert Response

Table 17. Configuration Register (00h) Settings for Figure 31 (Value = 6006h)

BIT # 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BIT
NAME		 RST — — — AVG2 AVG1 AVG0 VBUSCT2 VBUSCT1 VBUSCT0 ISHCT2 ISHCT1 ISHCT0 MODE3 MODE2 MODE1
POR VALUE 0 1 1 0 0 0 0 0 0 0 0 0 0 1 1 0

Table 18. Configuration Register (00h) Settings for Figure 32 (Value = 6126h)

BIT # 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BIT
NAME		 RST — — — AVG2 AVG1 AVG0 VBUSCT2 VBUSCT1 VBUSCT0 ISHCT2 ISHCT1 ISHCT0 MODE3 MODE2 MODE1
POR VALUE 0 1 1 0 0 0 0 1 0 0 1 0 0 1 1 0

Table 19. Mask/Enable Register (06h) Settings for Figure 31 and Figure 32 (Value = 2008h)

BIT # 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BIT
NAME		 OCL UCL BOL BUL POL CNVR — — — — — AFF CVRF OVF APOL LEN
POR VALUE 0 0 1 0 0 0 0 0 0 0 0 0 1 0 0 0

Table 20. Alert Limit Register (07h) Settings for Figure 31 and Figure 32 (Value = 1130h)

BIT # 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BIT
NAME		 AUL15 AUL14 AUL13 AUL12 AUL11 AUL10 AUL9 AUL8 AUL7 AUL6 AUL5 AUL4 AUL3 AUL2 AUL1 AUL0
POR VALUE 0 0 0 1 0 0 0 1 0 0 1 1 0 0 0 0