SBOS656C July   2016  – December 2016 INA260

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Related Products
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Integrated Shunt Resistor
      2. 8.3.2 Over-Current Capability
      3. 8.3.3 Basic ADC Functions
        1. 8.3.3.1 Power Calculation
        2. 8.3.3.2 ALERT Pin
    4. 8.4 Device Functional Modes
      1. 8.4.1 Averaging and Conversion Time Considerations
    5. 8.5 Programming
      1. 8.5.1 Calculating Returned Values
      2. 8.5.2 Default Settings
      3. 8.5.3 Communications Bus Overview
        1. 8.5.3.1 Serial Bus Address
        2. 8.5.3.2 Serial Interface
        3. 8.5.3.3 Writing to and Reading From the INA260
          1. 8.5.3.3.1 High-Speed I2C Mode
        4. 8.5.3.4 SMBus Alert Response
    6. 8.6 Register Maps
      1. 8.6.1 Configuration Register (00h) (Read/Write)
      2. 8.6.2 Current Register (01h) (Read-Only)
      3. 8.6.3 Bus Voltage Register (02h) (Read-Only)
      4. 8.6.4 Power Register (03h) (Read-Only)
      5. 8.6.5 Mask/Enable Register (06h) (Read/Write)
      6. 8.6.6 Alert Limit Register (07h) (Read/Write)
      7. 8.6.7 Manufacturer ID Register (FEh) (Read-Only)
      8. 8.6.8 Die ID Register (FFh) (Read-Only)
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Device Support
      1. 12.1.1 Third-Party Products Disclaimer
    2. 12.2 Documentation Support
      1. 12.2.1 Related Documentation
    3. 12.3 Receiving Notification of Documentation Updates
    4. 12.4 Community Resources
    5. 12.5 Trademarks
    6. 12.6 Electrostatic Discharge Caution
    7. 12.7 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7 Specifications

7.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)(1)
MIN MAX UNIT
Analog input current Continuous Conduction ±15 A
Analog inputs: IN+, IN– Common-mode (VIN+ + VIN–) / 2 –0.3 40 V
Voltage Supply, VS 6 V
VBUS pin –0.3 40
SDA, SCL, ALERT –0.3 6
Address Pins, A0, A1 –0.3 VS + 0.3
Open-drain digital output current, IOUT 10 mA
Temperature Junction, TJ 150 °C
Storage, Tstg –65 150
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

7.2 ESD Ratings

VALUE UNIT
V(ESD) Electrostatic discharge Human body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±2000 V
Charged device model (CDM), per JEDEC specification JESD22-C101(2) ±1000
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

7.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)
MIN NOM MAX UNIT
VCM Common-mode input voltage 0 36 V
VS Operating supply voltage 2.7 5.5 V
TA Operating free-air temperature –40 125 °C

7.4 Thermal Information

THERMAL METRIC(1) INA260 UNIT
PW (TSSOP)
16 PINS
RθJA Junction-to-ambient thermal resistance 115.6 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 50.1 °C/W
RθJB Junction-to-board thermal resistance 46.8 °C/W
ψJT Junction-to-top characterization parameter 3.3 °C/W
ψJB Junction-to-board characterization parameter 46.5 °C/W
RθJC(bot) Junction-to-case (bottom) thermal resistance N/A °C/W
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report, SPRA953.

7.5 Electrical Characteristics

at TA = 25°C, VS = 3.3 V, VIN+ = 12 V, VSENSE = (VIN+ – VIN–) = 0 mV and VVBUS = 12 V (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
INPUT
VCM Common-mode input range 0 36 V
Bus voltage input range(1) 0 36 V
CMRR Common-mode rejection 0 V ≤ VIN+ ≤ 36 V 0 150 µA/V
IOS Current sense offset, RTI(2) ±1.25 ±5 mA
Current sense offset drift, RTI(2) –40°C ≤ TA ≤ 125°C 1 50 µA/°C
PSRR Current sense offset voltage, RTI(2) vs power supply 2.7 V ≤ VS ≤ 5.5 V 1.6 3 mA/V
VOS Bus offset voltage, RTI(2) ±1.25 ±7.5 mV
Bus offset voltage, RTI(2) vs temperature –40°C ≤ TA ≤ 125°C 0.6 40 µV/°C
PSRR Bus offset voltage, RTI(2) vs power supply 1.5 mV/V
IB Input bias current (IIN+, IIN– pins) (IN+ pin) + (IN– pin), ISENSE = 0A 17 µA
VBUS input impedance 830 kΩ
Input leakage(3) (IN+ pin) + (IN– pin),
power-down mode		 0.1 0.5 µA
DC ACCURACY
System current sense gain error ISENSE = –15 A to 15 A, TA = 25°C 0.02% 0.15%
ISENSE = –10 A to 10 A,
–40°C ≤ TA ≤ 125°C		 0.2% 0.5%
–40°C ≤ TA ≤ 125°C 10 35 ppm/°C
Bus voltage gain error VBUS = 0 V to 36 V, TA = 25°C 0.02% 0.1%
VBUS = 0 V to 36 V,
–40°C ≤ TA ≤ 125°C		   0.1% 0.4%
–40°C ≤ TA ≤ 125°C 15 40 ppm/°C
INTEGRATED ADC
ADC native resolution 16 Bits
1-LSB step size Current 1.25 mA
Bus voltage 1.25 mV
Power​​​​ 10 mW
tCT ADC conversion time CT bit = 000 140 154 µs
CT bit = 001 204 224
CT bit = 010 332 365
CT bit = 011 588 646
CT bit = 100 1.1 1.21 ms
CT bit = 101 2.116 2.328
CT bit = 110 4.156 4.572
CT bit = 111 8.244 9.068
Differential nonlinearity ±0.1 LSB
INTEGRATED SHUNT
Package resistance IN+ to IN– 4.5 mΩ
Maximum continuous current –40°C ≤ TA ≤ 85°C ±15 A
Short time overload change ISENSE = 30 A for 5 seconds ±0.05%
Change due to thermal shock –65°C ≤ TA ≤ 150°C, 500 cycles ±0.1%
Resistance change to solder heat 260°C solder, 10 s ±0.1%
High temperature exposure change 1000 hours, TA = 150°C ±0.15%
Cold temperature storage change 24 hours, TA = –65°C ±0.025%
SMBus
SMBus timeout(4) 28 35 ms
DIGITAL INPUT/OUTPUT
Input capacitance 3 pF
Leakage input current 0 V ≤ VSCL ≤ VS, 0 V ≤ VSDA ≤ VS,
0 V ≤ VALERT ≤ VS, 0 V ≤ VA0 ≤ VS,
0 V ≤ VA1 ≤ VS		 0.1 1 µA
VIH High-level input voltage 0.7 × VS 6 V
VIL Low-level input voltage 0 0.3 × VS V
VOL Low-level output voltage, SDA, ALERT IOL = 3 mA 0 0.4 V
SDA, SCL Hysteresis  500 mV
POWER SUPPLY
Operating supply range 2.7 5.5 V
IQ Quiescent current 310 420 µA
Quiescent current, power-down (shutdown) mode 0.5 2 µA
VPOR Power-on reset threshold 2 V
(1) Although the input range is 36 V, the full-scale range of the ADC scaling is 40.96 V; see the Basic ADC Functions section. Do not apply more than 36 V.
(2) RTI = Referred-to-input.
(3) Input leakage is positive (current flowing into the pin) for the conditions shown at the top of this table. Negative leakage currents can occur under different input conditions.
(4) SMBus timeout in the INA260 resets the interface any time SCL is low for more than 28 ms.

7.6 Typical Characteristics

At TA = 25°C, VS = 3.3 V, VIN+ = 12 V, VSENSE = (VIN+ – VIN–) = 0 mV and VVBUS = 12 V, unless otherwise noted.
INA260 D011_SBOS656.gif
Figure 1. Current Sense Offset Production Distribution
INA260 D003_SBOS656.gif
Figure 3. Current Sense Common-Mode Rejection Ratio vs Temperature
INA260 D001_SBOS656.gif
Figure 5. Current Sense Gain Error vs Temperature
INA260 D013_SBOS656.gif
Figure 7. Bus Offset Voltage Production Distribution
INA260 tc_histo_bus_input_gain_err_distrib_bos547.gif
Figure 9. Bus Gain Error Production Distribution
INA260 D018_SBOS656.gif
Figure 11. Power Gain Error vs Temperature
INA260 g001_bos547.gif
Figure 13. Frequency Response
INA260 D006_SBOS656.gif
Figure 15. Input Bias Current vs Temperature (Both Inputs, IN+ and IN-)
INA260 D008_SBOS656.gif
Figure 17. Active IQ vs Temperature
INA260 D016_SBOS656.gif
Figure 19. Active IQ vs I2C Clock Frequency
INA260 D002_SBOS656.gif
Figure 2. Current Sense Offset vs Temperature
INA260 D012_SBOS656.gif Figure 4. Current Sense Gain Error Production Distribution
INA260 D015_SBOS656.gif
Figure 6. Current Sense Gain Error vs Common-Mode Voltage
INA260 D005_SBOS656.gif
Figure 8. Bus Offset Voltage vs Temperature
INA260 D004_SBOS656.gif
Figure 10. Bus Gain Error vs Temperature
INA260 D019_SBOS656.gif
Figure 12. Power Offset Error vs Temperature
INA260 D010_SBOS656.gif
Figure 14. Input Bias Current vs Common-Mode Voltage (Both Inputs, IN+ and IN-)
INA260 D007_SBOS656.gif
Figure 16. Input Bias Current vs Temperature, Shutdown (Both Inputs, IN+ and IN-)
INA260 D009_SBOS656.gif
Figure 18. Shutdown IQ vs Temperature
INA260 D017_SBOS656.gif
Figure 20. Shutdown IQ vs I2C Clock Frequency