SBOS764B December   2015  – December 2021 INA300-Q1

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Selecting a Current-Sensing Resistor
        1. 7.3.1.1 Selecting a Current-Sensing Resistor: Example
      2. 7.3.2 Setting The Current-Limit Threshold
        1. 7.3.2.1 Resistor-Controlled Current Limit
        2. 7.3.2.2 Voltage Source-Controlled Current Limit
      3. 7.3.3 Delay Setting
      4. 7.3.4 Alert Timing Response
      5. 7.3.5 Selectable Hysteresis
      6. 7.3.6 Alert Output
      7. 7.3.7 Noise Adjustment Factor (NAF)
    4. 7.4 Device Functional Modes
      1. 7.4.1 Alert Mode
        1. 7.4.1.1 Transparent Output Mode
        2. 7.4.1.2 Latch Output Mode
      2. 7.4.2 Disable Mode
      3. 7.4.3 Input Filtering
      4. 7.4.4 Using the INA300-Q1 INA300-Q1 With Common-Mode Transients Above 36 V
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Applications
      1. 8.2.1 Unidirectional Operation
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
        3. 8.2.1.3 Application Curve
      2. 8.2.2 Bidirectional Operation
        1. 8.2.2.1 Design Requirements
        2. 8.2.2.2 Detailed Design Procedure
        3. 8.2.2.3 Application Curve
      3. 8.2.3 Window Comparator
        1. 8.2.3.1 Design Requirements
        2. 8.2.3.2 Detailed Design Procedure
        3. 8.2.3.3 Application Curve
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 Receiving Notification of Documentation Updates
    3. 11.3 Support Resources
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7.3.7 Noise Adjustment Factor (NAF)

The device is a high-speed, low-noise comparator that is designed to alert when the measured input signal exceeds the programmed limit level. Internal noise in the device couples into the measurement and can result in alerts being issued prior to the input signal exceeding the voltage level present at the LIMIT terminal. This known internal noise component effects the input signal measurement by causing a consistent shift in the device internal offset, resulting in a shifted trip threshold. NAF adjusts the VLIMIT setting to account for this internal shift, thus allowing for a more precise level detection of the measured current.

The NAF value is based on the noise contribution on the measurement at the 10-µs delay setting. This value is equal to 500 µV and is applied in the calculation to adjust the VLIMIT threshold level to allow for a more accurate alert trip point. The NAF term is only applied in the VLIMIT calculation at the 10-µs delay setting. The averaging effect included with the 50-µs and 100-µs delay settings inherently eliminates the effect internal noise has on the threshold voltage. The NAF term can be omitted from the RLIMIT calculation at the 10-µs delay setting with the effect of a lower trigger point of the alert output. Lowering the trigger point results in an overcurrent alert prior to reaching the corresponding VTRIP threshold.