SBOS776C March   2016  – March 2021 INA3221-Q1

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Basic ADC Functions
      2. 8.3.2 Alert Monitoring
        1. 8.3.2.1 Critical Alert
          1. 8.3.2.1.1 Summation Control Function
        2. 8.3.2.2 Warning Alert
        3. 8.3.2.3 Power-Valid Alert
        4. 8.3.2.4 Timing-Control Alert
        5. 8.3.2.5 Default Settings
      3. 8.3.3 Software Reset
    4. 8.4 Device Functional Modes
      1. 8.4.1 Averaging Function
      2. 8.4.2 Multiple Channel Monitoring
        1. 8.4.2.1 Channel Configuration
        2. 8.4.2.2 Averaging and Conversion-Time Considerations
      3. 8.4.3 Filtering and Input Considerations
    5. 8.5 Programming
      1. 8.5.1 Bus Overview
        1. 8.5.1.1 Serial Bus Address
        2. 8.5.1.2 Serial Interface
      2. 8.5.2 Writing To and Reading From the INA3221-Q1
        1. 8.5.2.1 High-Speed I2C Mode
      3. 8.5.3 SMBus Alert Response
    6. 8.6 Register Maps
      1. 8.6.1 Summary of Register Set
      2. 8.6.2 Register Descriptions
        1. 8.6.2.1  Configuration Register (address = 00h) [reset = 7127h]
        2. 8.6.2.2  Channel-1 Shunt-Voltage Register (address = 01h), [reset = 00h]
        3. 8.6.2.3  Channel-1 Bus-Voltage Register (address = 02h) [reset = 00h]
        4. 8.6.2.4  Channel-2 Shunt-Voltage Register (address = 03h) [reset = 00h]
        5. 8.6.2.5  Channel-2 Bus-Voltage Register (address = 04h) [reset = 00h]
        6. 8.6.2.6  Channel-3 Shunt-Voltage Register (address = 05h) [reset = 00h]
        7. 8.6.2.7  Channel-3 Bus-Voltage Register (address = 06h) [reset = 00h]
        8. 8.6.2.8  Channel-1 Critical-Alert Limit Register (address = 07h) [reset = 7FF8h]
        9. 8.6.2.9  Warning-Alert Channel-1 Limit Register (address = 08h) [reset = 7FF8h]
        10. 8.6.2.10 Channel-2 Critical-Alert Limit Register (address = 09h) [reset = 7FF8h]
        11. 8.6.2.11 Channel-2 Warning-Alert Limit Register (address = 0Ah) [reset = 7FF8h]
        12. 8.6.2.12 Channel-3 Critical-Alert Limit Register (address = 0Bh) [reset = 7FF8h]
        13. 8.6.2.13 Channel-3 Warning-Alert Limit Register (address = 0Ch) [reset = 7FF8h]
        14. 8.6.2.14 Shunt-Voltage Sum Register (address = 0Dh) [reset = 00h]
        15. 8.6.2.15 Shunt-Voltage Sum-Limit Register (address = 0Eh) [reset = 7FFEh]
        16. 8.6.2.16 Mask/Enable Register (address = 0Fh) [reset = 0002h]
        17. 8.6.2.17 Power-Valid Upper-Limit Register (address = 10h) [reset = 2710h]
        18. 8.6.2.18 Power-Valid Lower-Limit Register (address = 11h) [reset = 2328h]
        19. 8.6.2.19 Manufacturer ID Register (address = FEh) [reset = 5449h]
        20. 8.6.2.20 Die ID Register (address = FFh) [reset = 3220]
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Device Support
      1. 12.1.1 Development Support
    2. 12.2 Documentation Support
      1. 12.2.1 Related Documentation
    3. 12.3 Receiving Notification of Documentation Updates
    4. 12.4 Support Resources
    5. 12.5 Trademarks
    6. 12.6 Electrostatic Discharge Caution
    7. 12.7 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

8.3.1 Basic ADC Functions

The INA3221-Q1 performs two measurements on up to three power supplies of interest. The voltage developed from the load current passing through a shunt resistor creates a shunt voltage that is measured between the IN+ and IN– pins. The device also internally measures the power-supply bus voltage at the IN– pin for each channel. The differential shunt voltage is measured with respect to the IN– pin, and the bus voltage is measured with respect to ground.

The INA3221-Q1 is typically powered by a separate power supply that ranges from 2.7 V to 5.5 V. The monitored supply buses range from 0 V to 26 V.

CAUTION:

Based on the fixed 8-mV bus-voltage register LSB (for any channel), a full-scale register value results in 32.76 V. However, the actual voltage applied to the INA3221-Q1 input pins must not exceed 26 V.

There are no special power-supply sequencing considerations between the common-mode input ranges and the device power-supply voltage because they are independent of each other; therefore, the bus voltages can be present with the supply voltage off and vice versa.

The INA3221-Q1 takes two measurements for each channel: one for shunt voltage and one for bus voltage. Each measurement can be independently or sequentially measured, based on the mode setting (bits 2-0 in the Configuration register). When the INA3221-Q1 is in normal operating mode (that is, the MODE bits of the Configuration register are set to 111), the device continuously converts a shunt-voltage reading followed by a bus-voltage reading. This procedure converts one channel, and then continues to the shunt voltage reading of the next enabled channel, followed by the bus-voltage reading for that channel, and so on, until all enabled channels have been measured. The programmed Configuration register mode setting applies to all channels. Any channels that are not enabled are bypassed in the measurement sequence, regardless of mode setting.

The INA3221-Q1 has two operating modes, continuous and single-shot, that determine the internal ADC operation after these conversions complete. When the INA3221-Q1 is set to continuous mode (using the MODE bit settings), the device continues to cycle through all enabled channels until a new configuration setting is programmed.

The Configuration register MODE control bits also enable modes to be selected that convert only the shunt or bus voltage. This feature further allows the device to fit specific application requirements.

In single-shot (triggered) mode, setting any single-shot convert mode to the Configuration register (that is, the Configuration register MODE bits set to 001, 010, or 011) triggers a single-shot conversion. This action produces a single set of measurements for all enabled channels. To trigger another single-shot conversion, write to the Configuration register a second time, even if the mode does not change. When a single-shot conversion is initiated, all enabled channels are measured one time and then the device enters a power-down state. The INA3221-Q1 registers can be read at any time, even while in power-down. The data present in these registers are from the last completed conversion results for the corresponding register. The conversion ready flag bit (Mask/Enable register, CVRF bit) helps coordinate single-shot conversions, and is especially helpful during longer conversion time settings. The CVRF bit is set after all conversions are complete. The CVRF bit clears under the following conditions:

  1. Writing to the Configuration register, except when configuring the MODE bits for power-down mode; or
  2. Reading the Mask/Enable register.

In addition to the two operating modes (continuous and single-shot), the INA3221-Q1 also has a separate selectable power-down mode that reduces the quiescent current and turns off current into the INA3221-Q1 inputs. Power-down mode reduces the impact of supply drain when the device is not used. Full recovery from power-down mode requires 40 µs. The INA3221-Q1 registers can be written to and read from while the device is in power-down mode. The device remains in power-down mode until one of the active MODE settings are written to the Configuration register.