SBOS776C March 2016 – March 2021 INA3221-Q1
PRODUCTION DATA
This register contains the value used to determine if the power-valid conditions are met. The power-valid condition is reached when all bus-voltage channels exceed the value set in this limit register. When the power-valid condition is met, the PV alert pin asserts high to indicate that the INA3221-Q1 has confirmed all bus voltage channels are above the power-valid upper-limit value. In order for the power-valid conditions to be monitored, the bus measurements must be enabled through one of the corresponding MODE bits set in the Configuration register. The power-valid upper-limit LSB value is 8 mV. Power-on reset value is 2710h = 10.000 V.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
SIGN | PVU11 | PVU10 | PVU9 | PVU8 | PVU7 | PVU6 | PVU5 | PVU4 | PVU3 | PVU2 | PVU1 | PVU0 | — | — | — |
RW-0 | RW-0 | RW-1 | RW-0 | RW-0 | RW-1 | RW-1 | RW-1 | RW-0 | RW-0 | RW-0 | RW-1 | RW-0 | RW-0 | RW-0 | RW-0 |
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15 | SIGN | R/W | 0h | Sign bit. 0 = positive number 1 = negative number in twos complement format |
14-3 | PVU11-0 | R/W | 4E2h | Power-valid upper-limit data bits |
2-0 | Reserved | R/W | 0h | Reserved |