SBOS776C March   2016  – March 2021 INA3221-Q1

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Basic ADC Functions
      2. 8.3.2 Alert Monitoring
        1. 8.3.2.1 Critical Alert
          1. 8.3.2.1.1 Summation Control Function
        2. 8.3.2.2 Warning Alert
        3. 8.3.2.3 Power-Valid Alert
        4. 8.3.2.4 Timing-Control Alert
        5. 8.3.2.5 Default Settings
      3. 8.3.3 Software Reset
    4. 8.4 Device Functional Modes
      1. 8.4.1 Averaging Function
      2. 8.4.2 Multiple Channel Monitoring
        1. 8.4.2.1 Channel Configuration
        2. 8.4.2.2 Averaging and Conversion-Time Considerations
      3. 8.4.3 Filtering and Input Considerations
    5. 8.5 Programming
      1. 8.5.1 Bus Overview
        1. 8.5.1.1 Serial Bus Address
        2. 8.5.1.2 Serial Interface
      2. 8.5.2 Writing To and Reading From the INA3221-Q1
        1. 8.5.2.1 High-Speed I2C Mode
      3. 8.5.3 SMBus Alert Response
    6. 8.6 Register Maps
      1. 8.6.1 Summary of Register Set
      2. 8.6.2 Register Descriptions
        1. 8.6.2.1  Configuration Register (address = 00h) [reset = 7127h]
        2. 8.6.2.2  Channel-1 Shunt-Voltage Register (address = 01h), [reset = 00h]
        3. 8.6.2.3  Channel-1 Bus-Voltage Register (address = 02h) [reset = 00h]
        4. 8.6.2.4  Channel-2 Shunt-Voltage Register (address = 03h) [reset = 00h]
        5. 8.6.2.5  Channel-2 Bus-Voltage Register (address = 04h) [reset = 00h]
        6. 8.6.2.6  Channel-3 Shunt-Voltage Register (address = 05h) [reset = 00h]
        7. 8.6.2.7  Channel-3 Bus-Voltage Register (address = 06h) [reset = 00h]
        8. 8.6.2.8  Channel-1 Critical-Alert Limit Register (address = 07h) [reset = 7FF8h]
        9. 8.6.2.9  Warning-Alert Channel-1 Limit Register (address = 08h) [reset = 7FF8h]
        10. 8.6.2.10 Channel-2 Critical-Alert Limit Register (address = 09h) [reset = 7FF8h]
        11. 8.6.2.11 Channel-2 Warning-Alert Limit Register (address = 0Ah) [reset = 7FF8h]
        12. 8.6.2.12 Channel-3 Critical-Alert Limit Register (address = 0Bh) [reset = 7FF8h]
        13. 8.6.2.13 Channel-3 Warning-Alert Limit Register (address = 0Ch) [reset = 7FF8h]
        14. 8.6.2.14 Shunt-Voltage Sum Register (address = 0Dh) [reset = 00h]
        15. 8.6.2.15 Shunt-Voltage Sum-Limit Register (address = 0Eh) [reset = 7FFEh]
        16. 8.6.2.16 Mask/Enable Register (address = 0Fh) [reset = 0002h]
        17. 8.6.2.17 Power-Valid Upper-Limit Register (address = 10h) [reset = 2710h]
        18. 8.6.2.18 Power-Valid Lower-Limit Register (address = 11h) [reset = 2328h]
        19. 8.6.2.19 Manufacturer ID Register (address = FEh) [reset = 5449h]
        20. 8.6.2.20 Die ID Register (address = FFh) [reset = 3220]
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Device Support
      1. 12.1.1 Development Support
    2. 12.2 Documentation Support
      1. 12.2.1 Related Documentation
    3. 12.3 Receiving Notification of Documentation Updates
    4. 12.4 Support Resources
    5. 12.5 Trademarks
    6. 12.6 Electrostatic Discharge Caution
    7. 12.7 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

8.6.2 Register Descriptions

All 16-bit INA3221-Q1 registers are two 8-bit bytes via the I2C interface. Table 8-4 shows a register map for the INA3221-Q1.

Table 8-4 Register Map
REGISTERADDRESS (Hex)D15D14D13D12D11D10D9D8D7D6D5D4D3D2D1D0
Configuration00RSTCH1enCH2enCH3enAVG2AVG1AVG0VBUSCT2VBUSCT1VBUSCT0VSHCT2VSHCT1VSHCT0MODE3MODE2MODE1
Channel-1 Shunt Voltage01SIGNSD11SD10SD9SD8SD7SD6SD5SD4SD3SD2SD1SD0———
Channel-1 Bus Voltage02SIGNBD11BD10BD9BD8BD7BD6BD5BD4BD3BD2BD1BD0———
Channel-2 Shunt Voltage03SIGNSD11SD10SD9SD8SD7SD6SD5SD4SD3SD2SD1SD0———
Channel-2 Bus Voltage04SIGNBD11BD10BD9BD8BD7BD6BD5BD4BD3BD2BD1BD0———
Channel-3 Shunt Voltage05SIGNSD11SD10SD9SD8SD7SD6SD5SD4SD3SD2SD1SD0———
Channel-3 Bus Voltage06SIGNBD11BD10BD9BD8BD7BD6BD5BD4BD3BD2BD1BD0———
Channel-1 Critical-Alert Limit07C1L12C1L11C1L10C1L9C1L8C1L7C1L6C1L5C1L4C1L3C1L2C1L1C1L0———
Channel-1 Warning-Alert Limit08W1L12W1L11W1L10W1L9W1L8W1L7W1L6W1L5W1L4W1L3W1L2W1L1W1L0———
Channel-2 Critical-Alert Limit09C2L12C2L11C2L10C2L9C2L8C2L7C2L6C2L5C2L4C2L3C2L2C2L1C2L0———
Channel-2 Warning-Alert Limit0AW2L12W2L11W2L10W2L9W2L8W2L7W2L6W2L5W2L4W2L3W2L2W2L1W2L0———
Channel-3 Critical-Alert Limit0BC3L12C3L11C3L10C3L9C3L8C3L7C3L6C3L5C3L4C3L3C3L2C3L1C3L0———
Channel-3 Warning-Alert Limit0CW3L12W3L11W3L10W3L9W3L8W3L7W3L6W3L5W3L4W3L3W3L2W3L1W3L0———
Shunt-Voltage Sum0DSIGNSV13SV12SV11SV10SV9SV8SV7SV6SV5SV4SV3SV2SV1SV0—
Shunt-Voltage Sum Limit0ESIGNSVL13SVL12SVL11SVL10SVL9SVL8SVL7SVL6SVL5SVL4SVL3SVL2SVL1SVL0—
Mask/Enable0F—SCC1SCC2SCC3WENCENCF1CF2CF3SFWF1WF2WF3PVFTCFCVRF
Power-Valid Upper Limit10PVU12PVU11PVU10PVU9PVU8PVU7PVU6PVU5PVU4PVU3PVU2PVU1PVU0———
Power-Valid Lower Limit11PVL12PVL11PVL10PVL9PVL8PVL7PVL6PVL5PVL4PVL3PVL2PVL1PVL0———
Manufacturer IDFE0101010001001001
Die IDFF0011001000100000