SBOSAD4 June   2024 INA4230

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Timing Requirements (I2C)
    7. 5.7 Timing Diagram
    8. 5.8 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 Integrated Analog-to-Digital Converter (ADC)
      2. 6.3.2 Internal Measurement and Calculation Engine
      3. 6.3.3 Low Bias Current
      4. 6.3.4 Low Voltage Supply and Wide Common-Mode Voltage Range
      5. 6.3.5 ALERT Pin
    4. 6.4 Device Functional Modes
      1. 6.4.1 Continuous Versus Triggered Operation
      2. 6.4.2 Device Low Power Modes
      3. 6.4.3 Power-On Reset
      4. 6.4.4 Averaging and Conversion Time Considerations
    5. 6.5 Programming
      1. 6.5.1 I2C Serial Interface
      2. 6.5.2 Writing to and Reading Through the I2C Serial Interface
      3. 6.5.3 High-Speed I2C Mode
      4. 6.5.4 General Call Reset
      5. 6.5.5 SMBus Alert Response
  8. 7 Register Maps
    1. 7.1 Device Registers
  9. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Device Measurement Range and Resolution
      2. 8.1.2 Current and Power Calculations
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Select the Shunt Resistor
        2. 8.2.2.2 Configure the Device
        3. 8.2.2.3 Program the Shunt Calibration Registers
        4. 8.2.2.4 Set Desired Fault Thresholds
        5. 8.2.2.5 Calculate Returned Values
      3. 8.2.3 Application Curves
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Device Support
      1. 9.1.1 Development Support
    2. 9.2 Documentation Support
      1. 9.2.1 Related Documentation
    3. 9.3 Receiving Notification of Documentation Updates
    4. 9.4 Support Resources
    5. 9.5 Trademarks
    6. 9.6 Electrostatic Discharge Caution
    7. 9.7 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
  • YBJ|16
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7.1 Device Registers

Table 7-1 lists the INA4230 registers. All register locations not listed in the table are considered as reserved locations and the register contents must not be modified.

Table 7-1 INA4230 Register Overview
Register NameAddressRegister TypeRegister Size (bits)Default Value
CONFIG10x20R/W160xF127
CONFIG20x21R/W160x0000
CALIBRATION_(CH1 - CH4)0x05,0x0D, 0x15. 0x1DR/W160x0000
ALERT_CONFIG(1 - 4)0x07, 0x0F, 0x17, 0x1FR/W160x0000
ALERT_LIMIT(1 - 4)0x06, 0x0E, 0x16, 0x1ER/W160x0000
SHUNT_VOLTAGE_(CH1 - CH4)0x00, 0x08, 0x10, 0x18R160x0000
BUS_VOLTAGE_(CH1 - CH4)0x01, 0x09, 0x11,0x19R160x0000
CURRENT_(CH1 - CH4)0x02, 0x0A, 0x12, 0x1AR160x0000
POWER_(CH1 - Ch4)0x03, 0x0B, 0x13, 0x1BR160x0000
ENERGY_(CH1 - CH4)0x04, 0x0C, 0x14, 0x1CR320x0000
FLAGS0x22R160x0000
MANUFACTURER_ID0x7ER160x5449 ("TI" in ASCII)

Complex bit access types are encoded to fit into small table cells. Table 7-2 shows the codes that are used for access types in this section.

Table 7-2 Device Access Type Codes
Access TypeCodeDescription
Read Type
RRRead
Write Type
WWWrite

7.1.1 CONFIG1 Register (Address = 0x20h) [reset = F127h]

The configuration register is shown in Table 7-3.

Table 7-3 CONFIG1 Register Field Descriptions
Bit Field Type Reset Description
15-12 ACTIVE_CHANNEL R/W 1111b These 4 bits determine which channels are active. Set this bit to '1' to enable each channel. Disabled channels are skipped in the round robin cycle.

Bit15 = Channel 4 measurement enable/disable.

Bit14 = Channel 3 measurement enable/disable.

Bit13 = Channel 2 measurement enable/disable.

Bit12 = Channel 1 measurement enable/disable.

Power up default: 1111b = All channels active
11-9 AVG R/W 000b Sets the number of ADC conversion results to be averaged. The read-back registers are updated after averaging is completed.

000b = 1

001b = 4

010b = 16

011b = 64

100b = 128

101b = 256

110b = 512

111b = 1024
8-6 VBUSCT R/W 100b Sets the conversion time of the VBUS measurement

000b = 140µs

001b = 204µs

010b = 332µs

011b = 588µs

100b = 1100µs

101b = 2116µs

110b = 4156µs

111b = 8244µs
5-3 VSHCT R/W

100b

 Sets the conversion time of the SHUNT measurement

000b = 140µs

001b = 204µs

010b = 332µs

011b = 588µs

100b = 1100µs

101b = 2116µs

110b = 4156µs

111b = 8244µs
2-0 MODE R/W

111b

 Operating mode, modes can be selected to operate the device either in Shutdown mode, continuous mode or triggered mode.
The mode also allows user to select mux settings to set continuous or triggered mode on bus voltage, shunt voltage measurement.

000b = Shutdown

001b = Shunt voltage triggered, single shot

010b = Bus voltage triggered, single shot

011b = Shunt voltage and Bus voltage triggered, single shot

100b = Shutdown

101b = Continuous shunt voltage

110b = Continuous bus voltage

111b = Continuous shunt and bus voltage

Return to the Summary Table.

7.1.2 CONFIG2 Register

The configuration register is shown in Table 7-4.

Table 7-4 CONFIG2 Register Field Descriptions
Bit Field Type Reset Description

15

RST

R/W

0b

Set this bit to '1' to generate a system reset that is the same as power-on reset.

Resets all registers to default values and then self-clears.
14-12 Reserved R 000b These bits always read 0.
11-8 ACC_RST R/W 0000b Writing a one to these bits resets the energy registers and clears any overflow flags.

Bit11 = Channel 4 energy reset, overflow clear.

Bit10 = Channel 3 energy reset, overflow clear.

Bit9 = Channel 2 energy reset, overflow clear.

Bit8 = Channel 1 energy reset, overflow clear.

Power up default: 0000b = All channels active

Bits are reset back to 0 after write.
7 CNVR_MASK R/W 0b

Setting this bit high configures the ALERT pin to be asserted when conversions are complete.

0b = Disable conversion ready flag on ALERT pin

1b = Enables conversion ready flag on ALERT pin

ALERT remains asserted until the CVRF field in the flags register is read.
6 ENOF_MASK R/W

0b

 When set to 1, the Alert pin toggles when an energy overflow condition occurs on any of the enabled channels
5 ALERT_LATCH R/W

0b

 When set to 1 the state of the Alert pin latches during fault conditions. To clear the alert the alert flags register must be read and the fault condition removed.
4 ALERT_POL R/W 0b When this bit is set to 1, the alert pin toggles from low to high during a fault condition. When set to 0 (default), the alert pin toggles from high to low during faults.
3-0 RANGE R/W 0000b

Enables the selection of the shunt full scale input range for each channel.

Bit3 = Channel 4 range selection.

Bit2 = Channel 3 range selection.

Bit1 = Channel 2 range selection.

Bit0 = Channel 1 range selection.

range selection bit = 0 selects ±81.92mV

range selection bit = 1 selects ±20.48mV

0000b = all channels set to ±81.92mV range

Return to the Summary Table.

7.1.3 CALIBRATION Registers

The calibration registers shown in Table 7-5 must be programmed to receive valid current, power, and energy results after initial power up, power cycle events, or on device enable.

Table 7-5 INA4230 Calibration Registers
Address Register Name Register Type Register Size (bits)
0x05 CALIBRATION_CH1 R/W 16
0x0D CALIBRATION_CH2 R/W 16
0x15 CALIBRATION_CH3 R/W 16
0x1D CALIBRATION_CH4 R/W 16

This register provides the device with the value of the shunt resistor that are present to create the measured differential voltage. This register also sets the resolution of the Current Register. Programming this register sets the Current_LSB and the Power_LSB.

Table 7-6 Calibration Register Field Descriptions
Bit Field Type Reset Description
15 Reserved R 0h
14-0 SHUNT_CAL R/W 0000h Programmed value needed for doing the shunt voltage to current conversion.

Return to the Summary Table.

7.1.4 Alert Configuration Registers

The alert configuration registers are shown in Table 7-7.

Table 7-7 INA4230 ALERT_CONFIG Registers
Address Register Name Register Type Register Size (bits)
0x07 ALERT1 R/W 16
0x0F ALERT2 R/W 16
0x17 ALERT3 R/W 16
0x1F ALERT4 R/W 16

The format of each alert configuration register is shown in Table 7-8.

These registers configure what triggers an alert for each of the channels. The alert mask field sets the active alert. Up to 4 alerts can be assigned to a given channel or spread equally across all channels depending on the needs of the application.

Table 7-8 Alert Configuration Register Field Descriptions
Bit Field Type Reset Description
15 - 4 Reserved R 000000000000b Reserved
4-3 CHANNEL R/W 00b Selects

00b = Channel 1

01b = Channel 2

10b = Channel 3

11b = Channel 4
2-0 ALERT_MASK

R/W

 000b Sets the active alert for the assigned channel

000b = reserved, no effect

001b = Shunt Voltage over limit (SOL)

010b = Shunt Voltage under limit (SUL)

011b = Bus Voltage over limit (BOL)

100b = Bus Voltage under limit (BUL)

101b = Power over limit (POL)

110b = reserved, no effect

111b = reserved, no effect

The alert configuration registers set what triggers an alert for each of the channels. The alert mask field sets the active alert. Up to 4 alerts can be assigned to a given channel or spread as required across all channels depending on the application.

Return to the Summary Table.

7.1.5 Alert Limit Registers

The alert limit registers shown in Table 7-9 must be programmed to set the desired fault limit threshold.

Table 7-9 INA4230 ALERT_LIMIT Registers
Address Register Name Register Type

Reset

 Register Size (bits)
0x06 LIMIT1 R/W

0000h

 16
0x0E LIMIT2 R/W

0000h

 16
0x16 LIMIT3 R/W

0000h

 16
0x1E LIMIT4 R/W

0000h

 16

The format of the alert limit register follows the format of the corresponding result register.

Shunt voltage limits are represented as signed 16 bit, bus voltage limits are unsigned 15 bit, and power limits are unsigned 16 bit values.

Return to the Summary Table.

7.1.6 Shunt Voltage Registers

The Shunt Voltage Registers store the current shunt voltage reading, VSHUNT. The shunt voltage measurement for each channel has a unique address as shown in Table 7-10.

Table 7-10 INA4230 SHUNT_VOLTAGE Registers
Address Register Name Register Type Register Size (bits)
0x00 SHUNT_VOLTAGE_CH1 R 16
0x08 SHUNT_VOLTAGE_CH2 R 16
0x10 SHUNT_VOLTAGE_CH3 R 16
0x18 SHUNT_VOLTAGE_CH4 R 16

The format of each shunt voltage register is shown in Table 7-11.

If averaging is enabled, these registers contain the averaged shunt voltage value.

Table 7-11 Shunt Voltage Register Field Description
Bit Field Type Reset Description
15-0 VSHUNT R 0000h Differential voltage measured across the shunt output. 2's complement value.

Negative numbers are represented in two's complement format. Generate the two's complement of a negative number by complementing the absolute value binary number and adding 1. An MSB = '1' denotes a negative number.

Example: For a value of VSHUNT = –80mV:

  1. Take the absolute value: 80mV
  2. Translate this number to a whole decimal number (80mV ÷ 2.5µV) = 32000
  3. Convert this number to binary = 0111 1101 0000 0000
  4. Complement the binary result = 1000 0010 1111 1111
  5. Add '1' to the complement to create the two's complement result = 1000 0011 0000 0000 = 8300h

Return to the Summary Table.

7.1.7 Bus Voltage Registers

The bus voltage registers store the voltage measured at the bus pin for each of the channels. Bus voltage measurements are stored in an unique register addresses as shown in Table 7-12.

Table 7-12 INA4230 BUS_VOLTAGE Registers
Address Register Name Register Type Register Size (bits)
0x01 BUS_VOLTAGE_CH1 R 16
0x09 BUS_VOLTAGE_CH2 R 16
0x11 BUS_VOLTAGE_CH3 R 16
0x19 BUS_VOLTAGE_CH4 R 16

The format of each bus voltage register is shown in Table 7-13.

The bus voltage registers only return positive values. If averaging is enabled, this register displays the averaged value.

Table 7-13 BUS_VOLTAGE Register Field Description
Bit Field Type Reset Description
15-0 VBUS R 0000h Bus voltage output. 2's complement value, however always positive.

Return to the Summary Table.

7.1.8 CURRENT Registers

The current registers store the calculated current value for each of the channels. Current measurements are stored in an unique register addresses as shown in Table 7-14.

Table 7-14 INA4230 CURRENT Registers
Address Register Name Register Type Register Size (bits)
0x02 CURRENT_CH1 R 16
0x0A CURRENT_CH2 R 16
0x12 CURRENT_CH3 R 16
0x1A CURRENT_CH4 R 16

The format of each bus current register is shown in Table 7-15.

If averaging is enabled, this register displays the averaged value. The value of the Current Register is calculated by multiplying the decimal value in the Shunt Voltage Register with the decimal value of the Calibration Register.

Table 7-15 CURRENT Register Field Description
Bit Field Type Reset Description
15-0 CURRENT R 0000h Calculated current output in Amperes. 2's complement value.

Return to the Summary Table.

7.1.9 POWER Registers

The power registers store the multiplied value of the bus voltage and current for each of the channels. Power measurements are stored in an unique register addresses as shown in Table 7-16.

Table 7-16 INA4230 POWER Registers
Address Register Name Register Type Register Size (bits)
0x03 POWER_CH1 R 16
0x0B POWER_CH2 R 16
0x13 POWER_CH3 R 16
0x1B POWER_CH4 R 16

The format of each bus power register is shown in Table 7-17.

If averaging is enabled, this register displays the averaged value. The Power Register records power in Watts by multiplying the decimal values of the Current Register with the decimal value of the Bus Voltage Register. This is an unsigned result.

Table 7-17 POWER Register Field Description
Bit Field Type Reset Description
15-0 POWER R 0000h This bit returns a calculated value of power in the system.
This is an unsigned result.

Return to the Summary Table.

7.1.10 Energy Registers

The energy registers accumulate data from the power registers and with the internal precision timebase calculate and store the energy for each of the channels. Energy measurements are stored in an unique register addresses as shown in Table 7-18.

Table 7-18 INA4230 ENERGY Registers
Address Register Name Register Type Register Size (bits)
0x04 ENERGY_CH1 R 32
0x0C ENERGY_CH2 R 32
0x14 ENERGY_CH3 R 32
0x1C ENERGY_CH4 R 32

The format of each bus power register is shown in Table 7-19.

The Energy register records energy in Joules and utilizes the precision oscillator as a timebase. This is an unsigned result.

Table 7-19 Energy Register Field Description
Bit Field Type Reset Description
31-0 ENERGY R 00000000h This bit returns a calculated value of energy in the system.
This is an unsigned result.

Return to the Summary Table.

7.1.11 Flags Register

The Flags Register is shown in Table 7-20.

Table 7-20 Flags Register Field Descriptions
Bit Field Type Reset Description
15 LIMIT4_ALERT R 0b

Indicates the fourth alert limit has been exceeded. This alert is independent of channel.
14 LIMIT3_ALERT R 0b

Indicates the third alert limit has been exceeded. This alert is independent of channel.
13 LIMIT2_ALERT R 0b

Indicates the second alert limit has been exceeded. This alert is independent of channel.
12 LIMIT1_ALERT R 0b

Indicates the first alert limit has been exceeded. This alert is independent of channel.
11 ENERGYOF_CH4 R 0b

Indicates an the energy register has overflowed for channel 4
10 ENERGYOF_CH3 R 0b

Indicates an the energy register has overflowed for channel 3
9 ENERGYOF_CH2 R 0b

Indicates an the energy register has overflowed for channel 2
8 ENERGYOF_CH1 R 0b

Indicates an the energy register has overflowed for channel 1
7 CVRF (Conversion Ready Flag) R 0b

Although the device can be read at any time, and the data from the last conversion is available, the Conversion Ready Flag bit is provided to help coordinate one-shot or triggered conversions.

The Conversion Ready Flag bit is set after all conversions, averaging, and multiplications are complete.

Conversion Ready Flag bit clears under the following conditions:

1.) Writing to the Configuration Register (except for Power-Down selection)

2.) Reading the Flags Register
6 OVF (Math Over-flow) R 0b This bit is set to '1' if an arithmetic operation results in an overflow error. This bit indicates that current and power data can be invalid.
5-0 Reserved - 000000b

Reserved

Return to the Summary Table.

7.1.12 Manufacturer ID Register (Address = 7Eh)

The manufacturer ID register is shown in Table 7-21.

Table 7-21 MANUFACTURE_ID Register Field Descriptions
Bit Field Type Reset Description
15-0 MANUFACTURE_ID R 5449h Reads back TI in ASCII

Return to the Summary Table.