SBOSAD4 June   2024 INA4230

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Timing Requirements (I2C)
    7. 5.7 Timing Diagram
    8. 5.8 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 Integrated Analog-to-Digital Converter (ADC)
      2. 6.3.2 Internal Measurement and Calculation Engine
      3. 6.3.3 Low Bias Current
      4. 6.3.4 Low Voltage Supply and Wide Common-Mode Voltage Range
      5. 6.3.5 ALERT Pin
    4. 6.4 Device Functional Modes
      1. 6.4.1 Continuous Versus Triggered Operation
      2. 6.4.2 Device Low Power Modes
      3. 6.4.3 Power-On Reset
      4. 6.4.4 Averaging and Conversion Time Considerations
    5. 6.5 Programming
      1. 6.5.1 I2C Serial Interface
      2. 6.5.2 Writing to and Reading Through the I2C Serial Interface
      3. 6.5.3 High-Speed I2C Mode
      4. 6.5.4 General Call Reset
      5. 6.5.5 SMBus Alert Response
  8. 7 Register Maps
    1. 7.1 Device Registers
  9. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Device Measurement Range and Resolution
      2. 8.1.2 Current and Power Calculations
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Select the Shunt Resistor
        2. 8.2.2.2 Configure the Device
        3. 8.2.2.3 Program the Shunt Calibration Registers
        4. 8.2.2.4 Set Desired Fault Thresholds
        5. 8.2.2.5 Calculate Returned Values
      3. 8.2.3 Application Curves
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Device Support
      1. 9.1.1 Development Support
    2. 9.2 Documentation Support
      1. 9.2.1 Related Documentation
    3. 9.3 Receiving Notification of Documentation Updates
    4. 9.4 Support Resources
    5. 9.5 Trademarks
    6. 9.6 Electrostatic Discharge Caution
    7. 9.7 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6.5.2 Writing to and Reading Through the I2C Serial Interface

Accessing a specific register on the INA4230 is accomplished by writing the appropriate value to the register pointer. Refer to Register Maps for a complete list of registers and corresponding addresses. The value for the register pointer (see Figure 6-5) is the first byte transferred after the target address byte with the R/W bit low. Every write operation to the device requires a value for the register pointer.

Writing to a register begins with the first byte transmitted by the controller. This byte is the target address, with the R/W bit low. The device then acknowledges receipt of a valid address. The next byte transmitted by the controller is the address of the register to be accessed. This register address value updates the register pointer to the desired internal device register. The next two bytes are written to the register addressed by the register pointer. The device acknowledges receipt of each data byte. The controller can terminate data transfer by generating a start or stop condition.

When reading from the device, the last value stored in the register pointer by a write operation determines which register is read during a read operation. To change the register pointer for a read operation, a new value must be written to the register pointer. This write is accomplished by issuing a target address byte with the R/W bit low, followed by the register pointer byte. No additional data are required. The controller then generates a start condition and sends the address byte for the target with the R/W bit high to initiate the read command. The next byte is transmitted by the target and is the most significant byte of the register indicated by the register pointer. This byte is followed by an Acknowledge from the controller; then the target transmits the least significant byte. The controller can or can not acknowledge receipt of the second data byte. The controller can terminate data transfer by generating a Not-Acknowledge after receiving any data byte, or generating a start or stop condition. If repeated reads from the same register are desired, continually sending the register pointer bytes is not necessary. The device retains the register pointer value until the value is changed by the next write operation.

Figure 6-3 shows the write operation timing diagram. Figure 6-4 shows the read operation timing diagram. These diagrams are shown for reading/writing to 16 bit registers.

Register bytes are sent most-significant byte first, followed by the least significant byte.

INA4230 Timing Diagram for Write Word Format
A. The value of the Target Address byte is determined by the setting of the A0 address pin. Refer to Table 6-1.
B. The device does not support packet error checking (PEC) or perform clock stretching.
Figure 6-3 Timing Diagram for Write Word Format
INA4230 Timing Diagram for Read Word Format
A. The value of the Target Address byte is determined by the setting of the A0 address pin. Refer to Table 6-1.
B. Read data is from the last register pointer location. If a new register is desired, the register pointer must be updated. See Figure 6-5.
C. ACK by the controller can also be sent.
D. The device does not support packet error checking (PEC) or perform clock stretching.
Figure 6-4 Timing Diagram for Read Word Format
INA4230 Typical Register Pointer Set
A. The value of the Target Address byte is determined by the setting of the A0 address pin. Refer to Table 6-1.
Figure 6-5 Typical Register Pointer Set