SBOSAD4 June   2024 INA4230

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Timing Requirements (I2C)
    7. 5.7 Timing Diagram
    8. 5.8 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 Integrated Analog-to-Digital Converter (ADC)
      2. 6.3.2 Internal Measurement and Calculation Engine
      3. 6.3.3 Low Bias Current
      4. 6.3.4 Low Voltage Supply and Wide Common-Mode Voltage Range
      5. 6.3.5 ALERT Pin
    4. 6.4 Device Functional Modes
      1. 6.4.1 Continuous Versus Triggered Operation
      2. 6.4.2 Device Low Power Modes
      3. 6.4.3 Power-On Reset
      4. 6.4.4 Averaging and Conversion Time Considerations
    5. 6.5 Programming
      1. 6.5.1 I2C Serial Interface
      2. 6.5.2 Writing to and Reading Through the I2C Serial Interface
      3. 6.5.3 High-Speed I2C Mode
      4. 6.5.4 General Call Reset
      5. 6.5.5 SMBus Alert Response
  8. 7 Register Maps
    1. 7.1 Device Registers
  9. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Device Measurement Range and Resolution
      2. 8.1.2 Current and Power Calculations
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Select the Shunt Resistor
        2. 8.2.2.2 Configure the Device
        3. 8.2.2.3 Program the Shunt Calibration Registers
        4. 8.2.2.4 Set Desired Fault Thresholds
        5. 8.2.2.5 Calculate Returned Values
      3. 8.2.3 Application Curves
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Device Support
      1. 9.1.1 Development Support
    2. 9.2 Documentation Support
      1. 9.2.1 Related Documentation
    3. 9.3 Receiving Notification of Documentation Updates
    4. 9.4 Support Resources
    5. 9.5 Trademarks
    6. 9.6 Electrostatic Discharge Caution
    7. 9.7 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

5.5 Electrical Characteristics

at TA = 25°C, VS = 3.3V, VSENSE = VIN+ - VIN- = 0mV, VIN- = VBUS = 12V, for all channels (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
INPUT
CMRR Common-mode rejection VCM = –0.3V to 48V, TA = –40°C to 125°C 110 120 dB
Shunt voltage input range ADCRANGE = 0 –81.9175 81.92 mV
ADCRANGE = 1 –20.4794 20.48 mV
Vos Shunt offset voltage VCM = 12 V ±10 ±75 µV
dVos/dT Shunt offset voltage drift TA = –40°C to 125°C ±0.1 ±0.5 µV/°C
Vos_b IN- bus offset Voltage ±5 ±30 mV
dVos_b/dT IN- bus offset voltage drift TA = –40°C to 125°C ±10 ±30 µV/°C
PSRRSH Power supply rejection ratio
(Current measurments)		 VS = 1.7V to 5.5V, TA = –40°C to 125°C ±0.2 ±2.5 µV/V
PSRRBUS Power supply rejection ratio
(Voltage measurments)		 VS = 1.7V to 5.5V, TA = –40°C to 125°C ±0.5 ±2.5 mV/V
ZIN- IN- input impedance Bus Voltage Measurement Mode 1.05 MΩ
IB Input bias current IN+, IN-, Current Measurment Mode 0.1 5 nA
DC ACCURACY
RDIFF Differential Input Impedance
(IN+ to IN-)		 VIN+ - VIN- < 82mV  140 kΩ
ADC Resolution TA = –40°C to 125°C 16 Bits
1 LSB step size Shunt Voltage 2.5 µV
Bus Voltage 1.6 mV
ADC Conversion-time
(TA = –40°C to 125°C)		 CT bit = 000 140 µs
CT bit = 001 204 µs
CT bit = 010 332 µs
CT bit = 011 588 µs
CT bit = 100 1.100 ms
CT bit = 101 2.116 ms
CT bit = 110 4.156 ms
CT bit = 111 8.244 ms
Internal Oscillator Frequency TA = +25°C 500 kHz
Internal Oscillator Tolerance TA = +25°C 0.5 %
TA = –40°C to +125°C 1 %
GSERR Shunt voltage gain error ±0.02 ±0.75 %
GS_DRFT Shunt voltage gain error drift TA = –40°C to +125°C 50 ppm/°C
GBERR VIN- voltage gain error ±0.02 ±0.75 %
GB_DRFT VIN- voltage gain error drift TA = –40°C to +125°C 50 ppm/°C
PTME Power total measurement error At full scale voltage and current ±0.04 ±1.5 %
ETME Energy total measurement error At full scale voltage and current ±0.3 ±2 %
INL Integral Non-Linearity ADCRANGE = 0, Linear best fit,TA = –40°C to +125°C ±2 ±6 m%
DNL Differential Non-Linearity ±0.1 LSB
ENABLE
IEN Input leakage current 0 V ≤ VEN ≤ VS 1 50 nA
VIH Logic input level, high VS = 1.7V to 3.6V, TA = –40°C to +125°C 1.1 5.5 V
VIH Logic input level, high VS = 3.6V to 5.5V, TA = –40°C to +125°C 1.3 5.5 V
VIL Logic input level, low VS = 1.7V to 5.5V, TA = –40°C to +125°C 0 0.4 V
VHYS Hysteresis 50 mV
POWER SUPPLY
IQ Quiescent current 400 500 µA
IQ vs temperature, TA = –40°C to +125°C 600 µA
Shutdown 2.5 4 µA
IQ Quiescent current disabled VEN = 0V  0.15 1 µA
VPOR Power-on reset threshold VS falling 0.95 V
SMBUS
SMBUS timeout 28 35 ms
Input capacitance 3 pF
DIGITAL INTERFACE
VIH Logic input level, high VS = 1.7V to 5.5V, TA = –40°C to +125°C 0.9 5.5 V
VIL Logic input level, low VS = 1.7V to 5.5V, TA = –40°C to +125°C 0 0.4 V
VHYS Hysteresis 130 mV
VOL Logic output level, low IOL = 3mA, VS = 1.7V to 5.5V, TA = –40°C to +125°C 0 0.3 V
Digital leakage input current 0 ≤ VINPUT ≤ VS  ±50 nA