SBOSAI9 Data sheet

SBOSAI9B December 2023 – March 2024 INA500

PRODMIX

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)

DBV|6
DCK|6

Thermal pad, mechanical data (Package|Pins)

Orderable Information

6.8 Typical Characteristics

at T_A = 25°C, V_S = (V+) – (V–) = 5.5V, V_IN = (V_IN+ – V_IN–) = 0V, R_L = 10kΩ, C_L = 10pF, V_REF = V_S / 2, V_CM = (V_IN+ + V_IN–) / 2 = V_S / 2, V_OUT = V_S / 2 and G = 1 (unless otherwise noted)

G = 1

N = 31

μ = ̶ 5.78μV

σ = 0.670mV

Figure 6-1 Typical Distribution of Output Referred Offset Voltage

G = 0.25

N = 35

μ = 42.74μV

σ = 0.336mV

Figure 6-3 Typical Distribution of Output Referred Offset Voltage

G = 0.5

N = 35

μ = 0.72μV/°C

σ = 0.43μV/°C

Figure 6-5 Typical Distribution of Output Referred Offset Drift

G = 1

N = 31

μ = 13.30μV/V

σ = 28.25μV/V

Figure 6-7 Typical Distribution of Output Referred CMRR

G = 0.25

N = 35

μ = 3.49μV/V

σ = 15.46μV/V

Figure 6-9 Typical Distribution of Output Referred CMRR

G = 0.5

N = 35

μ = 0.028%

σ = 0.019%

Figure 6-11 Typical Distribution of Gain Error

G = 1

N = 31

μ = ̶ 0.003%

σ = 0.002%

Figure 6-13 Typical Distribution of Reference Gain Error

N = 35

G = 0.5

Figure 6-15 Output Referred Offset Voltage vs Temperature

Figure 6-17 Quiescent Current vs Temperature

G = 1

Figure 6-19 Output Referred CMRR vs Temperature

G = 1

V+ = 2.75V and V– = –2.75V

N = 31

Figure 6-21 Output Referred Offset Voltage vs Input Common-Mode Voltage

G = 0.25

V+ = 2.75V and V– = –2.75V

N = 35

Figure 6-23 Output Referred Offset Voltage vs Input Common-Mode Voltage

G = 0.5

V+ = 1.65V and V– = –1.65V

N = 35

Figure 6-25 Output Referred Offset Voltage vs Input Common-Mode Voltage

G = 1

V+ = 2.75V and V– = –2.75V

Figure 6-27 Quiescent Current vs Input Common-Mode Voltage

G = 0.25

V+ = 2.75V and V– = –2.75V

Figure 6-29 Quiescent Current vs Input Common-Mode Voltage

N = 32

G = 0.5

Figure 6-31 Output Referred Offset Voltage vs Supply Voltage

V+ = 2.5V and V– = –2.5V

V+ = 1.65V and V– = –1.65V

Figure 6-33 Output Voltage vs Output Current (Sourcing)

Figure 6-35 Closed-Loop Gain vs Frequency

Figure 6-37 PSRR+ (Referred to Output) vs Frequency

Figure 6-39 Output Referred Voltage Noise Spectral Density

G = 0.5

Figure 6-41 Output Referred 0.1 Hz to 10 Hz Voltage Noise in Time Domain

Figure 6-43 Closed-Loop Output Impedance vs Frequency

V_S = 5.5V	BW = 80kHz	V_CM = 2.75V
R_L = 10kΩ	V_OUT = 0.5V_RMS	G = 1

Figure 6-45 THD + N Frequency

Figure 6-47 Electromagnetic Interference Rejection Ratio Referred to Output vs Frequency (Differential Input)

V+ = 2.75V

V– = –2.75V

G = 1

V_OUT = 4V_PP

Figure 6-49 Large Signal Step Response

V+ = 2.75V

V– = –2.75V

G = 1

V_OUT = 4V_PP

Figure 6-51 Large Signal Settling Time (Rising Edge)

V+ = 2.75V

V– = –2.75V

G = 0.5

V_OUT = 4V_PP

Figure 6-53 Large Signal Settling Time (Falling Edge)

V+ = 2.75V

V– = –2.75V

G = 0.25

V_OUT = 4V_PP

Figure 6-55 Large Signal Step Response

V+ = 2.75V

V– = –2.75V

G = 0.25

V_OUT = 4V_PP

Figure 6-57 Large Signal Settling Time (Rising Edge)

V+ = 2.75V

V– = –2.75V

G = 0.5

V_OUT = 100mV_PP

Figure 6-59 Small-Signal Step Response

V_S = 5.5V

G = 1

V_OUT = 100mV_PP

Figure 6-61 Small-Signal Overshoot vs Capacitive Load

V_S = 5.5V	G = 0.25	V_OUT = 100mV_PP

Figure 6-63 Small-Signal Overshoot vs Capacitive Load

V+ = 2.75V

V– = –2.75V

G = 1

V_IN = 6V_PP

Figure 6-65 No Phase Reversal

V+ = 5.5V

V– = 0V

G = 0.5

V_REF = 0V

Figure 6-67 Input Common-Mode Voltage vs Output Voltage (High CMRR Region)

V+ = 5.5V

V– = 0V

G = 0.25

V_REF = 0V

Figure 6-69 Input Common-Mode Voltage vs Output Voltage (Rail-to-Rail CMRR Region)

V+ = 5.5V	V– = 0V	G = 1	V_REF = 0V

Figure 6-71 Input Common-Mode Voltage vs Output Voltage (Rail-to-Rail CMRR Region)

V+ = 5.5V

V– = 0V

G = 0.5

V_REF = 2.75V

Figure 6-73 Input Common-Mode Voltage vs Output Voltage (High CMRR Region)

V+ = 5.5V

V– = 0V

G = 0.25

V_REF = 2.75V

Figure 6-75 Input Common-Mode Voltage vs Output Voltage (Rail-to-Rail CMRR Region)

V+ = 5.5V

V– = 0V

G = 1

V_REF = 2.75V

Figure 6-77 Input Common-Mode Voltage vs Output Voltage (Rail-to-Rail CMRR Region)

G = 0.5

N = 35

μ = ̶ 6.43μV

σ = 0.430mV

Figure 6-2 Typical Distribution of Output Referred Offset Voltage

G = 1

N = 31

μ = 0.95μV/°C

σ = 0.60μV/°C

Figure 6-4 Typical Distribution of Output Referred Offset Drift

G = 0.25

N = 35

μ = 0.70μV/°C

σ = 0.45μV/°C

Figure 6-6 Typical Distribution of Output Referred Offset Drift

G = 0.5

N = 35

μ = 9.90μV/V

σ = 16.30μV/V

Figure 6-8 Typical Distribution of Output Referred CMRR

G = 1

N = 31

μ = 0.01%

σ = 0.003%

Figure 6-10 Typical Distribution of Gain Error

G = 0.25

N = 35

μ = 0.025%

σ = 0.021%

Figure 6-12 Typical Distribution of Gain Error

N = 31	G = 1

Figure 6-14 Output Referred Offset Voltage vs Temperature

N = 35

G = 0.25

Figure 6-16 Output Referred Offset Voltage vs Temperature

G = 1

Figure 6-18 Gain Error vs Temperature

V+ = 2.75V and V– = –2.75V

Figure 6-20 Short-Circuit Current vs Temperature

G = 0.5

V+ = 2.75V and V– = –2.75V

N = 35

Figure 6-22 Output Referred Offset Voltage vs Input Common-Mode Voltage

G = 1

V+ = 1.65V and V– = –1.65V

N = 31

Figure 6-24 Output Referred Offset Voltage vs Input Common-Mode Voltage

G = 0.25

V+ = 1.65V and V– = –1.65V

N = 35

Figure 6-26 Output Referred Offset Voltage vs Input Common-Mode Voltage

G = 0.5

V+ = 2.75V and V– = –2.75V

Figure 6-28 Quiescent Current vs Input Common-Mode Voltage

N = 31

G = 1

Figure 6-30 Output Referred Offset Voltage vs Supply Voltage

N = 32

G = 0.25

Figure 6-32 Output Referred Offset Voltage vs Supply Voltage

V+ = 2.5V and V– = –2.5V

V+ = 1.65V and V– = –1.65V

Figure 6-34 Output Voltage vs Output Current (Sinking)

Figure 6-36 CMRR (Referred to Output) vs Frequency

Figure 6-38 PSRR– (Referred to Output) Vs Frequency

G = 1

Figure 6-40 Output Referred 0.1 Hz to 10 Hz Voltage Noise in Time Domain

G = 0.25

Figure 6-42 Output Referred 0.1 Hz to 10 Hz Voltage Noise in Time Domain

Figure 6-44 Maximum Output Voltage vs Frequency

V_S = 5.5V	BW = 80kHz	V_CM = 2.75V
R_L = 100kΩ	V_OUT = 1V_RMS	G = 1

Figure 6-46 THD + N Frequency

Figure 6-48 Electromagnetic Interference Rejection Ratio Referred to Output vs Frequency (Common-Mode Input)

V+ = 2.75V

V– = –2.75V

G = 1

V_OUT = 4V_PP

Figure 6-50 Large Signal Settling Time (Falling Edge)

V+ = 2.75V

V– = –2.75V

G = 0.5

V_OUT = 4V_PP

Figure 6-52 Large Signal Step Response

V+ = 2.75V

V– = –2.75V

G = 0.5

V_OUT = 4V_PP

Figure 6-54 Large Signal Settling Time (Rising Edge)

V+ = 2.75V

V– = –2.75V

G = 0.25

V_OUT = 4V_PP

Figure 6-56 Large Signal Settling Time (Falling Edge)

V+ = 2.75V

V– = –2.75V

G = 1

V_OUT = 100mV_PP

Figure 6-58 Small-Signal Step Response

V+ = 2.75V

V– = –2.75V

G = 0.25

V_OUT = 100mV_PP

Figure 6-60 Small-Signal Step Response

V_S = 5.5V

G = 0.5

V_OUT = 100mV_PP

Figure 6-62 Small-Signal Overshoot vs Capacitive Load

V+ = 2.75V

V– = –2.75V

G = 1

V_IN = 6V_PP

Figure 6-64 Over-Load Recovery

V+ = 5.5V

V– = 0V

G = 0.25

V_REF = 0V

Figure 6-66 Input Common-Mode Voltage vs Output Voltage (High CMRR Region)

V+ = 5.5V

V– = 0V

G = 1

V_REF = 0V

Figure 6-68 Input Common-Mode Voltage vs Output Voltage (High CMRR Region)

V+ = 5.5V

V– = 0V

G = 0.5

V_REF = 0V

Figure 6-70 Input Common-Mode Voltage vs Output Voltage (Rail-to-Rail CMRR Region)

V+ = 5.5V

V– = 0V

G = 0.25

V_REF = 2.75V

Figure 6-72 Input Common-Mode Voltage vs Output Voltage (High CMRR Region)

V+ = 5.5V

V– = 0V

G = 1

V_REF = 2.75V

Figure 6-74 Input Common-Mode Voltage vs Output Voltage (High CMRR Region)

V+ = 5.5V

V– = 0V

G = 0.5

V_REF = 2.75V

Figure 6-76 Input Common-Mode Voltage vs Output Voltage (Rail-to-Rail CMRR Region)