SBOSAB4A May   2023  – September 2023 INA700

PRODUCTION DATA  

  1.   1
  2. Features
  3. Applications
  4. Description
  5. Revision History
  6. Pin Configuration and Functions
  7. Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements (I2C)
    7. 6.7 Timing Diagram
    8. 6.8 Typical Characteristics
  8. Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Integrated Shunt Resistor
      2. 7.3.2 Safe Operating Area
      3. 7.3.3 Versatile Measurement Capability
      4. 7.3.4 Internal Measurement and Calculation Engine
      5. 7.3.5 High-Precision Delta-Sigma ADC
        1. 7.3.5.1 Low Latency Digital Filter
        2. 7.3.5.2 Flexible Conversion Times and Averaging
      6. 7.3.6 Integrated Precision Oscillator
      7. 7.3.7 Multi-Alert Monitoring and Fault Detection
    4. 7.4 Device Functional Modes
      1. 7.4.1 Shutdown Mode
      2. 7.4.2 Power-On Reset
    5. 7.5 Programming
      1. 7.5.1 I2C Serial Interface
        1. 7.5.1.1 Writing to and Reading Through the I2C Serial Interface
        2. 7.5.1.2 High-Speed I2C Mode
        3. 7.5.1.3 SMBus Alert Response
    6. 7.6 Register Maps
      1. 7.6.1 INA700 Registers
  9. Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Device Measurement Range and Resolution
      2. 8.1.2 ADC Output Data Rate and Noise Performance
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Configure the Device
        2. 8.2.2.2 Set Desired Fault Thresholds
        3. 8.2.2.3 Calculate Returned Values
      3. 8.2.3 Application Curves
  10. Power Supply Recommendations
  11. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  12. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 Receiving Notification of Documentation Updates
    3. 11.3 Support Resources
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  13. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

SMBus Alert Response

The INA700 is designed to respond to the SMBus Alert Response address. The SMBus Alert Response provides a quick fault identification for simple secondary devices. When an Alert occurs, the main device can broadcast the Alert Response secondary device address (0001 100) with the R/W bit set high. Following this Alert Response, any secondary device that generates an alert can identify itself by acknowledging the Alert Response and sending its address to the bus.

The Alert Response can activate several different target devices simultaneously, similar to the I2C General Call. If more than one target attempts to respond, bus arbitration rules apply. The losing device does not generate an Acknowledge and continues to hold the Alert line low until that device wins arbitration.