SBOSAC3A July   2023  – December 2023 INA745A , INA745B

PRODMIX  

  1.   1
  2. Features
  3. Applications
  4. Description
  5. Pin Configuration and Functions
  6. Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Timing Requirements (I2C)
    7. 5.7 Timing Diagram
    8. 5.8 Typical Characteristics
  7. Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 Integrated Shunt Resistor
      2. 6.3.2 Safe Operating Area
      3. 6.3.3 Versatile Measurement Capability
      4. 6.3.4 Internal Measurement and Calculation Engine
      5. 6.3.5 High-Precision Delta-Sigma ADC
        1. 6.3.5.1 Low Latency Digital Filter
        2. 6.3.5.2 Flexible Conversion Times and Averaging
      6. 6.3.6 Integrated Precision Oscillator
      7. 6.3.7 Multi-Alert Monitoring and Fault Detection
    4. 6.4 Device Functional Modes
      1. 6.4.1 Shutdown Mode
      2. 6.4.2 Power-On Reset
    5. 6.5 Programming
      1. 6.5.1 I2C Serial Interface
        1. 6.5.1.1 Writing to and Reading Through the I2C Serial Interface
        2. 6.5.1.2 High-Speed I2C Mode
        3. 6.5.1.3 SMBus Alert Response
  8. Application and Implementation
    1. 7.1 Application Information
      1. 7.1.1 Device Measurement Range and Resolution
      2. 7.1.2 ADC Output Data Rate and Noise Performance
    2. 7.2 Typical Application
      1. 7.2.1 Design Requirements
      2. 7.2.2 Detailed Design Procedure
        1. 7.2.2.1 Configure the Device
        2. 7.2.2.2 Set Desired Fault Thresholds
        3. 7.2.2.3 Calculate Returned Values
      3. 7.2.3 Application Curves
    3. 7.3 Power Supply Recommendations
    4. 7.4 Layout
      1. 7.4.1 Layout Guidelines
      2. 7.4.2 Layout Example
    5. 7.5 Register Maps
      1. 7.5.1 INA745x Registers
  9. Device and Documentation Support
    1. 8.1 Receiving Notification of Documentation Updates
    2. 8.2 Support Resources
    3. 8.3 Trademarks
    4. 8.4 Electrostatic Discharge Caution
    5. 8.5 Glossary
  10. Revision History
  11. 10Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

I2C Serial Interface

The INA745x operates only as a target on both the SMBus and I2C interfaces. Connections to the bus are made through the open-drain SDA and SCL lines. The SDA and SCL pins feature integrated spike suppression filters and Schmitt triggers to minimize the effects of input spikes and bus noise. Although the device integrates spike suppression into the digital I/O lines, proper layout techniques help minimize the amount of coupling into the communication lines. This noise introduction can occur from capacitive coupling signal edges between the two communication lines themselves or from other switching noise sources present in the system. Routing traces in parallel with ground in between layers on a printed circuit board (PCB) typically reduces the effects of coupling between the communication lines. Shielded communication lines reduce the possibility of unintended noise coupling into the digital I/O lines that could be incorrectly interpreted as start or stop commands.

The INA745x supports the transmission protocol for fast mode (1 kHz to 400 kHz) and high-speed mode (1 kHz to 2.94 MHz). All data bytes are transmitted most significant byte first and follow the SMBus 3.0 transfer protocol.

To communicate with the INA745x, the controller must first address targets through a target address byte. The target address byte consists of seven address bits and a direction bit that indicates whether the action is to be a read or write operation.

The device has two address pins, A0 and A1. Table 6-2 lists the pin logic levels for each of the 16 possible addresses. The device samples the state of pins A0 and A1 on every bus communication. Establish the pin state before any activity on the interface occurs. When connecting the SDA pin to either A0 or A1 to set the device address, an additional hold time of 100 ns is required on the MSB of the I2C address to ensure correct device addressing.

Table 6-2 Address Pins and Target Addresses
A1A0TARGET DEVICE ADDRESS
GNDGND1000000
GNDVS1000001
GNDSDA1000010(1)
GNDSCL1000011
VSGND1000100
VSVS1000101
VSSDA1000110(1)
VSSCL1000111
SDAGND1001000(1)
SDAVS1001001(1)
SDASDA1001010(1)
SDASCL1001011(1)
SCLGND1001100
SCLVS1001101
SCLSDA1001110(1)
SCLSCL1001111
Any address using SDA will require an initial hold time of 100 ns on the MSB of the address.