SBOS894A April   2019  – June 2019 INA818

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
    1.     Device Images
      1.      INA818 Simplified Internal Schematic
      2.      Typical Distribution of Input Stage Offset Voltage Drift
  4. 4 Revision History
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
    1.     Pin Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Typical Characteristics: Table of Graphs
    7. 7.7 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Setting the Gain
        1. 8.3.1.1 Gain Drift
      2. 8.3.2 EMI Rejection
      3. 8.3.3 Input Common-Mode Range
      4. 8.3.4 Input Protection
      5. 8.3.5 Operating Voltage
      6. 8.3.6 Error Sources
    4. 8.4 Device Functional Modes
  9. 9 Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 Reference Pin
      2. 9.1.2 Input Bias Current Return Path
    2. 9.2 Typical Applications
      1. 9.2.1 Three-Pin Programmable Logic Controller (PLC)
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
        3. 9.2.1.3 Application Curves
      2. 9.2.2 Resistance Temperature Detector Interface
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Documentation Support
      1. 12.1.1 Related Documentation
    2. 12.2 Receiving Notification of Documentation Updates
    3. 12.3 Community Resources
    4. 12.4 Trademarks
    5. 12.5 Electrostatic Discharge Caution
    6. 12.6 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7.5 Electrical Characteristics

at TA = 25°C, VS = ±15 V, RL = 10 kΩ, VREF = 0 V, and G = 1 (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
INPUT
VOSI Input stage offset voltage(1)(3) 10 35 µV
TA = –40°C to 125°C(2) 75 µV
drift vs temperature, TA = –40°C to 125°C 0.4 µV/°C
VOSO Output stage offset voltage(1)(3) 50 300 µV
TA = –40°C to 125°C(2) 800 µV
drift vs temperature, TA = –40°C to 125°C 5 µV/°C
PSRR Power-supply rejection ratio G = 1, RTI 110 120 dB
G = 10, RTI 114 130
G = 100, RTI 130 135
G = 1000, RTI 136 140
zid Differential impedance 100 || 1 GΩ || pF
zic Common-mode impedance 100 || 4 GΩ || pF
RFI filter, –3-dB frequency 32 MHz
VCM Operating input range(4) (V–) + 2 (V+) – 2 V
VS = ±2.25 V to ±18 V, TA = –40°C to 125°C See Figure 51 to Figure 54
Input overvoltage range TA = –40°C to 125°C(2) ±60 V
CMRR Common-mode rejection ratio At DC to 60 Hz, RTI, VCM = (V–) + 2 V to (V+) – 2 V,
G = 1		 90 105 dB
At DC to 60 Hz, RTI, VCM = (V–) + 2 V to (V+) – 2 V,
G = 10		 110 125
At DC to 60 Hz, RTI, VCM = (V–) + 2 V to (V+) – 2 V,
G = 100		 130 145
At DC to 60 Hz, RTI, VCM = (V–) + 2 V to (V+) – 2 V,
G = 1000		 140 150
BIAS CURRENT
IB Input bias current VCM = VS / 2 0.15 0.5 nA
TA = –40°C to 125°C 2
IOS Input offset current VCM = VS / 2 0.15 0.5 nA
TA = –40°C to 125°C 2
NOISE VOLTAGE
eNI Input stage voltage noise(6) f = 1 kHz, G = 100, RS = 0 Ω 8 nV/√Hz
fB = 0.1 Hz to 10 Hz, G = 100, RS = 0 Ω 0.19 µVPP
eNO Output stage voltage noise(6) f = 1 kHz, RS = 0 Ω 80 nV/√Hz
fB = 0.1 Hz to 10 Hz, RS = 0 Ω 2.6 µVPP
In Noise current f = 1 kHz 130 fA/√Hz
fB = 0.1 Hz to 10 Hz, G = 100 4.7 pAPP
GAIN
Gain equation 1 + (50 kΩ / RG) V/V
G Gain 1 1000 V/V
GE Gain error G = 1, VO = ±10 V ±0.005% ±0.025%
G = 10, VO = ±10 V ±0.025% ±0.15%
G = 100, VO = ±10 V ±0.025% ±0.15%
G = 1000, VO = ±10 V ±0.05%
Gain error drift(5) G = 1, TA = –40°C to 125°C, VO = ±10 V ±5 ppm/°C
G > 1, TA = –40°C to 125°C, VO = ±10 V ±35
Gain nonlinearity G = 1 to 10, VO = –10 V to 10 V, RL = 10 kΩ 1 10 ppm
G = 100, VO = –10 V to 10 V, RL = 10 kΩ 15
G = 1000, VO = –10 V to 10 V, RL = 10 kΩ 10
G = 1 to 100, VO = –10 V to 10 V, RL = 2 kΩ 30
OUTPUT
Voltage swing (V–) + 0.15 (V+) – 0.15 V
Load capacitance stability 1000 pF
ZO Closed-loop output impedance f = 10 kHz 5.0 Ω
ISC Short-circuit current Continuous to VS / 2 ±20 mA
FREQUENCY RESPONSE
BW Bandwidth, –3 dB G = 1 2.0 MHz
G = 10 890 kHz
G = 100 270
G = 1000 30
SR Slew rate G = 1, VO = ±10 V 0.9 V/µs
tS Settling time 0.01%, G = 1 to 100, VSTEP = 10 V 12 µs
0.01%, G = 1000, VSTEP = 10 V 40
0.001%, G = 1 to 100, VSTEP = 10 V 16
0.001%, G = 1000, VSTEP = 10 V 60
REFERENCE INPUT
RIN Input impedance 40 kΩ
Voltage range (V–) (V+) V
Gain to output 1 V/V
Reference gain error 0.01%
POWER SUPPLY
IQ Quiescent current VIN = 0 V 350 385 µA
VIN = 0 V, TA = –40°C to 125°C 520
(1) Total offset, referred-to-input (RTI): VOS = (VOSI) + (VOSO / G).
(2) Specified by characterization.
(3) Offset drifts are uncorrelated. Input-referred offset drift is calculated using: ΔVOS(RTI) = √[ΔVOSI2 + (ΔVOSO / G)2]
(4) Input voltage range of the INA818 input stage. The input range depends on the common-mode voltage, differential voltage, gain, and reference voltage. See Typical Characteristic curves Figure 51 through Figure 54 for more information.
(5) The values specified for G > 1 do not include the effects of the external gain-setting resistor, RG.
(6) Total RTI voltage noise is equal to: eN(RTI) = √[eNI2 + (eNO / G)2]