7.3.1 Inside the INA826S

See the Functional Block Diagram section for a simplified representation of the INA826S. A more detailed diagram (shown in Figure 65) provides additional details of the INA826S operation.

Each input is protected by two field-effect transistors (FETs) that provide a low series resistance under normal signal conditions, and preserve excellent noise performance. When excessive voltage is applied, these transistors limit input current to approximately 8 mA.

The differential input voltage is buffered by Q₁ and Q₂ and is impressed across R_G, causing a signal current to flow through R_G, R₁, and R₂. The output difference amplifier, A₃, removes the common-mode component of the input signal and refers the output signal to the REF pin.

The equations shown in Figure 65 describe the output voltages of A₁ and A₂. The V_BE and voltage drop across R₁ and R₂ produce output voltages on A₁ and A₂ that are approximately 0.8 V higher than the input voltages.

Figure 65. INA826S Simplified Circuit Diagram

7.3.2 Setting the Gain

Gain of the INA826S is set by a single external resistor, R_G, connected between pins 2 and 3. Use Equation 1 to select the value of R_G:

Equation 1.

Table 1 lists several commonly-used gains and resistor values. The 49.4-kΩ term in Equation 1 comes from the sum of the two internal 24.7-kΩ feedback resistors. These on-chip resistors are laser-trimmed to accurate absolute values. The accuracy and temperature coefficients of these resistors are included in the gain accuracy and drift specifications of the INA826S.

7.3.3 Offset Trimming

Most applications require no external offset adjustment; however, if necessary, adjustments can be made by applying a voltage to the REF pin. Figure 66 shows an optional circuit for trimming the output offset voltage. The voltage applied to the REF pin is summed at the output. The op amp buffer provides low impedance at the REF pin to preserve good common-mode rejection.

Figure 66. Optional Trimming of Output Offset Voltage

7.3.4 Input Common-Mode Range

The linear input voltage range of the INA826S input circuitry extends from the negative supply voltage to 1 V below the positive supply, and maintains 84-dB (minimum) common-mode rejection throughout this range. The common-mode range for most common operating conditions is described in Figure 12 through Figure 18 and Figure 44 through Figure 46. The INA826S can operate over a wide range of power supplies and V_REF configurations, making a comprehensive guide to common-mode range limits impractical to be provided for all possible conditions.

The most commonly overlooked overload condition occurs when a circuit exceeds the output swing of A₁ and A₂, which are internal circuit nodes that cannot be measured. Calculating the expected voltages at the output of A₁ and A₂ (see Figure 65) provides a check for the most common overload conditions. The designs of A₁ and A₂ are identical and the outputs can swing to within approximately 100 mV of the power-supply rails. For example, when the A₂ output is saturated, A₁ may continue to be in linear operation, responding to changes in the noninverting input voltage. This difference can give the appearance of linear operation but the output voltage is invalid.

A single-supply instrumentation amplifier has special design considerations. To achieve a common-mode range that extends to single-supply ground, the INA826S employs a current-feedback topology with PNP input transistors; see Figure 65. The matched PNP transistors Q₁ and Q₂ shift the input voltages of both inputs up by a diode drop, and through the feedback network, shift the output of A₁ and A₂ by approximately 0.8 V. With both inputs and V_REF at single-supply ground (negative power supply), the output of A₁ and A₂ is well within the linear range, allowing differential measurements to be made at the GND level. As a result of this input level-shifting, the voltages at pin 2 and pin 3 are not equal to the respective input pin voltages (pin 1 and pin 4). For most applications, this inequality is not important because only the gain-setting resistor connects to these pins.

7.3.5 Input Protection

The inputs of the INA826S are individually protected for voltages up to ±40 V. For example, a condition of –40 V on one input and 40 V on the other input does not cause damage. However, if the input voltage exceeds (V–) – 2 V and the signal source current drive capability exceeds 3.5 mA, the output voltage switches to the opposite polarity; see Figure 20. This polarity reversal can easily be avoided by adding resistance of 10 kΩ in series with both inputs.

Internal circuitry on each input provides low series impedance under normal signal conditions. If the input is overloaded, the protection circuitry limits the input current to a safe value of approximately 8 mA. Figure 20 and Figure 21 illustrate this input current limit behavior. The inputs are protected even if the power supplies are disconnected or turned off.

7.3.6 Input Bias Current Return Path

The input impedance of the INA826S is extremely high—approximately 20 GΩ. However, a path must be provided for the input bias current of both inputs. This input bias current is typically 35 nA. High input impedance means that this input bias current changes very little with varying input voltage.

Input circuitry must provide a path for this input bias current for proper operation. Figure 67 shows various provisions for an input bias current path. Without a bias current path, the inputs float to a potential that exceeds the common-mode range of the INA826S, and the input amplifiers saturate. If the differential source resistance is low, as shown in the thermocouple example in Figure 67, the bias current return path can be connected to one input. With higher source impedance, using two equal resistors provides a balanced input with possible advantages of lower input offset voltage as a result of bias current and better high-frequency common-mode rejection.

Figure 67. Providing an Input Common-Mode Current Path

7.3.7 Reference Pin (REF)

The output voltage of the INA826S is developed with respect to the voltage on the reference terminal. Often, in dual-supply operation, the reference pin (pin 6) is connected to the low-impedance system ground. In single-supply operation, offsetting the output signal to a precise mid-supply level can be useful (for example, 2.5 V in a 5-V supply environment). To accomplish this offset, a voltage source can be tied to the REF pin to level-shift the output so that the INA826S can drive a single-supply ADC, for example.

For the best performance, keep the source impedance to the REF pin below 5 Ω. As shown in , the reference resistor is at one end of a 50-kΩ resistor. Additional impedance at the REF pin adds to this 50-kΩ resistor. The imbalance in the resistor ratios results in degraded common-mode rejection ratio (CMRR).

Figure 68 shows two different methods of driving the reference pin with low impedance. The OPA330 is a low-power, chopper-stabilized amplifier, and therefore offers excellent stability over temperature. The OPA330 is available in the space-saving SC70 and even smaller chip-scale package. The REF3225 is a precision reference in the small SOT23-6 package.

Figure 68. Options for Low-Impedance Level Shifting

7.3.8 Shutdown (EN and ENREF) Pins

The INA826S provides two pins to shut the device down: EN (enable) and ENREF (enable reference). Figure 69 shows a basic schematic of the shutdown logic circuitry of the INA826S. A PNP transistor forms the basis of the internal shutdown circuitry. The ENREF pin is connected to the emitter of the PNP transistor and is meant to be connected to a voltage reference point for the enable logic. The EN pin is connected the base of the PNP transistor. Applying a voltage to the EN pin that is 0.8 V or more below the enable reference voltage (at the ENREF pin) causes a small current to flow in the internal PNP transistor that powers the INA826S internal bias circuitry and powers-up the instrumentation amplifier. The shutdown circuitry functions properly with ENREF connected to a voltage between (V–) + 1.5 V up to V+. The voltage on the EN pin can be as low as the negative supply voltage (VS–) but cannot go above the voltage applied to the ENREF pin.

Figure 69. Shutdown Pin Simplified Schematic

To better understand the functionality of these pins, consider the low-voltage, single-supply application shown in Figure 70 with V+ = 3.3 V. ENREF is connected to the 3.3-V power supply of the microcontroller (labeled µC) and the EN pin is toggled by a general-purpose input/output (GPIO) pin of the microcontroller. When the GPIO pin is asserted low, such that the voltage at the GPIO pin output is at or near 0 V, the INA826S is enabled. Conversely, if the GPIO pin is asserted high, with an output voltage at or near 3.3 V, the INA826S is disabled.

Figure 70. Example Configuration in a Single-Supply System
(Pulling EN low enables the INA826S.)

Figure 71 shows an alternate configuration of the enable logic pins. By grounding the enable pin, and toggling the ENREF pin with the GPIO of the microcontroller, the enable logic is reversed. Now asserting high at the GPIO output enables the INA826S, and pulling the GPIO pin low disables the INA826S.

Figure 71. Alternate Configuration for the Enable Logic Pins
(Pulling ENREF high enables the INA826S.)

The majority of INA826S applications benefit greatly from the reduction of quiescent current from the typical 200 µA to values at or below 6 µA. Achieving the lowest possible system-level current in a system requires attention to other system voltages applied to the INA826S. When shutdown, voltages applied to the reference or input pins of the INA826S can find paths for currents to flow up into the several microamps region. In many systems these voltages are shut down when the INA826S is shutdown, simplifying the problem. Otherwise, additional switching may be added to reduce currents to a minimum.