SBOS945B November   2020  – April 2021 INA849

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Adjustable Gain Setting
      2. 8.3.2 Gain Drift
      3. 8.3.3 Wide Input Common-Mode Range
    4. 8.4 Device Functional Modes
  9. 9 Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 Reference Pin
      2. 9.1.2 Input Bias Current Return Path
      3. 9.1.3 Thermal Effects due to Power Dissipation
    2. 9.2 Typical Application
      1. 9.2.1 Sensor Conditioning Circuit
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
      2. 9.2.2 Phantom Power in Microphone Preamplifier Circuit
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Documentation Support
      1. 12.1.1 Related Documentation
    2. 12.2 Receiving Notification of Documentation Updates
    3. 12.3 Support Resources
    4. 12.4 Trademarks
    5. 12.5 Electrostatic Discharge Caution
    6. 12.6 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

9.1.1 Reference Pin

The output voltage of the INA849 is developed with respect to the voltage on reference pin REF.

Use the REF pin to offset the output signal to a precise midsupply level. Typically, this offset is 2.5 V in a 5-V supply environment. To accomplish this level shift, a voltage source must be connected to the REF pin to level-shift the output so that the INA849 drives a single-supply analog-to-digital converter (ADC).

For dual-supply operation, the reference pin is typically connected to the low-impedance system ground.

The voltage source applied to the reference pin must have a low output impedance. As shown in Figure 9-1, any resistance at the reference pin (shown as RREF) is in series with an internal 5-kΩ resistor that creates an imbalance in the four resistors of the internal difference amplifier.

GUID-20201014-CA0I-ZVXG-7BMP-NGMBFRH297G4-low.gif Figure 9-1 Parasitic Resistance Shown at the Reference Pin

This imbalance results in a degraded common-mode rejection ratio (CMRR). Figure 9-2 shows how the common-mode rejection ratio degrades depending on the source resistance on the reference pin. For best performance, keep the dc CMRR greater than 100 dB by keeping the source impedance to the REF pin (represented as R1) to less than 0.1 Ω.

GUID-20201203-CA0I-ZCWL-J7HS-DDVJK5ZM7VGX-low.svg Figure 9-2 Effect of Parasitic Resistance at the Reference Pin

Voltage-reference devices are an excellent option for providing a low-impedance voltage source for the reference pin. However, if a resistor voltage divider generates a reference voltage, the divider must be buffered by an op amp (as Figure 9-3 shows) to avoid CMRR degradation.

GUID-20201014-CA0I-WBCQ-PXLD-R7B89PLDPMGJ-low.gif Figure 9-3 Using an Op Amp to Buffer Reference Voltages