at
TA = 25°C, VS = ±15 V, VCM at mid-supply,
VRL = 10 kΩ, connected to ground, VREF = 0 V, and G = 1
(unless otherwise noted)
| N = 1695, mean = 0.26 µV, std
dev = 5.85 µV |
Figure 7-1 Typical Distribution of Input Offset Voltage
| N = 1695, mean = -43.83 µV,
std dev = 111.74 µV |
Figure 7-3 Typical Distribution of Output Offset Voltage
| N = 120, mean = 7.58 nA, std
dev = 1.84 nA |
Figure 7-5 Typical Distribution of Input Bias Current 
| N = 120, mean = -0.11 nA, std
dev = 1.01 nA |
Figure 7-7 Typical Distribution of Input Offset Current
| N = 120, mean = -0.375 µV/V,
std dev = 0.043 µV/V |
Figure 7-9 Typical CMRR Distribution G = 100
Figure 7-11 Output Stage Offset Voltage vs Temperature
Figure 7-13 Output-referred Offset
Voltage vs Negative Input Common-Mode Voltage
Figure 7-15 Positive Input Bias
Current vs Input Common-Mode Voltage
Figure 7-17 Input Offset Current vs
Input Common-Mode Voltage
Figure 7-19 Input Offset Current vs
Temperature
Figure 7-21 CMRR
vs Frequency (1-kΩ source imbalance)
Figure 7-23 Negative PSRR vs Frequency (RTI)
Figure 7-25 Current Noise Spectral Density vs Frequency (RTI)
Figure 7-27 0.1-Hz to 10-Hz RTI Voltage Noise
Figure 7-29 Gain
Nonlinearity vs Output Voltage
Figure 7-31 Closed-Loop Gain vs Frequency
Figure 7-33 Large-Signal Frequency Response
Figure 7-35 Small-Signal Step Response at G = 1
Figure 7-37 Small-Signal Step Response at G = 100
Figure 7-39 Settling Time for G = 1
Figure 7-41 Settling Time for G = 1000 
Figure 7-43 Total
Harmonic Distortion vs Frequency at Different Loads
Figure 7-45 Third
Harmonic Distortion vs Frequency
| N = 30, mean = 0.10 µV/°C,
std dev = 0.08 µV/°C |
Figure 7-2 Typical Distribution of Input Offset Voltage Drift
| N = 120, mean = -4.14 µV/°C,
std dev = 2.00 µV/°C |
Figure 7-4 Typical Distribution of Output Offset Voltage Drift
| N = 120, mean = 7.24 nA, std
dev = 1.80 nA |
Figure 7-6 Typical Distribution of Input Bias Current at 85°C 
| N = 120, mean = 3.08 µV/V,
std dev = 5.57 µV/V |
Figure 7-8 Typical CMRR Distribution G = 1
Figure 7-10 Input
Stage Offset Voltage vs Temperature
Figure 7-12 Boundary Plot - Input Common-Mode Voltage vs Output Voltage
Figure 7-14 Output-referred Offset
Voltage vs Positive Input Common-Mode Voltage
Figure 7-16 Negative Input Bias
Current vs Input Common-Mode Voltage
Figure 7-18 Input Bias Current vs
Temperature
Figure 7-20 CMRR
vs Frequency (RTI)
Figure 7-22 Positive PSRR vs Frequency (RTI)
Figure 7-24 Voltage Noise Spectral Density vs Frequency (RTI)
Figure 7-26 0.1-Hz to 10-Hz RTI Voltage Noise
Figure 7-28 0.1-Hz to 10-Hz RTI Current Noise
Figure 7-30 Gain Nonlinearity vs Output Voltage
Figure 7-32 Closed-Loop Output Impedance vs Frequency
Figure 7-34 Overshoot vs Capacitive Loads
Figure 7-36 Small-Signal Step Response at G = 10
Figure 7-38 Small-Signal Step Response at G = 1000
Figure 7-40 Settling Time for G = 100
Figure 7-42 Total
Harmonic Distortion vs Frequency
Figure 7-44 Second Harmonic Distortion vs Frequency
Figure 7-46 Supply Current vs Temperature