SBOS945B November   2020  – April 2021 INA849

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Adjustable Gain Setting
      2. 8.3.2 Gain Drift
      3. 8.3.3 Wide Input Common-Mode Range
    4. 8.4 Device Functional Modes
  9. 9 Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 Reference Pin
      2. 9.1.2 Input Bias Current Return Path
      3. 9.1.3 Thermal Effects due to Power Dissipation
    2. 9.2 Typical Application
      1. 9.2.1 Sensor Conditioning Circuit
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
      2. 9.2.2 Phantom Power in Microphone Preamplifier Circuit
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Documentation Support
      1. 12.1.1 Related Documentation
    2. 12.2 Receiving Notification of Documentation Updates
    3. 12.3 Support Resources
    4. 12.4 Trademarks
    5. 12.5 Electrostatic Discharge Caution
    6. 12.6 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

11.1 Layout Guidelines

Use good PCB layout practices for best operational performance of the device, including:

  • To avoid converting common-mode signals into differential signals and thermal electromotive forces (EMFs), make sure that both input paths are symmetrical and well-matched for source impedance and capacitance.
  • Place the external gain resistor close to the RG pins to keep the loop inductance as low as possible and to avoid a potential parasitic coupling path, but also so that capacitance mismatch between the RG pins is minimized.
  • Noise can propagate into analog circuitry through the power pins of the circuit as a whole and of the device. Bypass capacitors reduce the coupled noise by providing low-impedance power sources local to the analog circuitry.
    • Connect low-ESR, 0.1-µF, ceramic bypass capacitors between each supply pin and ground, placed as close as possible to the device.
    • A single bypass capacitor from V+ to ground is applicable for single-supply applications.
  • To reduce parasitic coupling, run the input traces as far away as possible from the supply or output traces. If these traces cannot be kept separate, crossing the sensitive trace perpendicular is much better than in parallel with the noisy trace.
  • Keep traces as short as possible.
  • Minimize the number of thermal junctions. Ideally, the signal path is routed within a single layer without vias.
  • Keep sufficient distance from major thermal energy sources (circuits with high power dissipation). If not possible, place the device such that it matches the thermal energy source on the differential signal path.