SBOS999A March   2022  – October 2022 INA851

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Related Products
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Adjustable Gain Setting
        1. 8.3.1.1 Gain Drift
      2. 8.3.2 Offset Voltage
      3. 8.3.3 Input Common-Mode Range
      4. 8.3.4 Input Protection
      5. 8.3.5 Output Clamping
      6. 8.3.6 Low Noise
    4. 8.4 Device Functional Modes
  9. 9 Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 Output Common-Mode Pin
      2. 9.1.2 Output-Stage Gain Selection and Noise-Gain Shaping
      3. 9.1.3 Input Bias Current Return Path
      4. 9.1.4 Thermal Effects due to Power Dissipation
    2. 9.2 Typical Applications
      1. 9.2.1 Three-Pin Programmable Logic Controller (PLC)
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
        3. 9.2.1.3 Application Curves
      2. 9.2.2 20-Bit, 1-MSPS ADS8900B Driver Circuit With FDA Noise Filter
        1. 9.2.2.1 Design Requirements
        2. 9.2.2.2 Application Curves
      3. 9.2.3 24-Bit, 200 kSPS, Delta-Sigma ADS127L11 ADC Driver Circuit With FDA Noise Filter
        1. 9.2.3.1 Design Requirements
        2. 9.2.3.2 Application Curves
    3. 9.3 Power Supply Recommendations
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
      2. 9.4.2 Layout Example
  10. 10Device and Documentation Support
    1. 10.1 Device Support
      1. 10.1.1 Development Support
        1. 10.1.1.1 PSpice® for TI
        2. 10.1.1.2 TINA-TI™ Simulation Software (Free Download)
    2. 10.2 Documentation Support
      1. 10.2.1 Related Documentation
    3. 10.3 Receiving Notification of Documentation Updates
    4. 10.4 Support Resources
    5. 10.5 Trademarks
    6. 10.6 Electrostatic Discharge Caution
    7. 10.7 Glossary
  11. 11Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

8.3.1.1 Gain Drift

The stability and temperature drift of external gain setting resistor RG also affects gain. The contribution of RG to gain accuracy and drift is determined from Equation 1. The best gain drift of 5 ppm/℃ (maximum) is achieved when the INA851 uses G = 1 in the input stage, without RG connected. In this case, gain drift is limited by the mismatch of the temperature coefficient of the integrated resistors in fully differential amplifier A3. When the output stage is in attenuating gain mode (OUT− shorted to G02− and OUT+ shorted to G02+), both the 1.25-kΩ and the 5-kΩ resistors contribute mismatch, as do the traces between the G02x and OUTx pins. Only the 5-kΩ resistors contribute mismatch when the output stage is in unity gain mode (with G02− and G02+ floating).

At input stage gains greater than 1, gain drift increases as a result of the individual drift of the 3-kΩ resistors in the feedback of A1 and A2, relative to the drift of external gain resistor RG. The low temperature coefficient of the internal feedback resistors improves the overall temperature stability of applications using input-stage gains greater than 1 V/V over alternate solutions. The low resistor values required for high gain make wiring resistance an important consideration. Sockets add to the wiring resistance and contribute additional gain error (such as a possible unstable gain error) at gains of approximately 20 or greater. To maintain stability, avoid parasitic capacitance of more than a few picofarads at the RG connections. Careful matching of any parasitics on the RG pins maintains optimal CMRR over frequency.