SBOS999A March   2022  – October 2022 INA851

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Related Products
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Adjustable Gain Setting
        1. 8.3.1.1 Gain Drift
      2. 8.3.2 Offset Voltage
      3. 8.3.3 Input Common-Mode Range
      4. 8.3.4 Input Protection
      5. 8.3.5 Output Clamping
      6. 8.3.6 Low Noise
    4. 8.4 Device Functional Modes
  9. 9 Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 Output Common-Mode Pin
      2. 9.1.2 Output-Stage Gain Selection and Noise-Gain Shaping
      3. 9.1.3 Input Bias Current Return Path
      4. 9.1.4 Thermal Effects due to Power Dissipation
    2. 9.2 Typical Applications
      1. 9.2.1 Three-Pin Programmable Logic Controller (PLC)
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
        3. 9.2.1.3 Application Curves
      2. 9.2.2 20-Bit, 1-MSPS ADS8900B Driver Circuit With FDA Noise Filter
        1. 9.2.2.1 Design Requirements
        2. 9.2.2.2 Application Curves
      3. 9.2.3 24-Bit, 200 kSPS, Delta-Sigma ADS127L11 ADC Driver Circuit With FDA Noise Filter
        1. 9.2.3.1 Design Requirements
        2. 9.2.3.2 Application Curves
    3. 9.3 Power Supply Recommendations
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
      2. 9.4.2 Layout Example
  10. 10Device and Documentation Support
    1. 10.1 Device Support
      1. 10.1.1 Development Support
        1. 10.1.1.1 PSpice® for TI
        2. 10.1.1.2 TINA-TI™ Simulation Software (Free Download)
    2. 10.2 Documentation Support
      1. 10.2.1 Related Documentation
    3. 10.3 Receiving Notification of Documentation Updates
    4. 10.4 Support Resources
    5. 10.5 Trademarks
    6. 10.6 Electrostatic Discharge Caution
    7. 10.7 Glossary
  11. 11Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

9.2.2.2 Application Curves

Table 9-2 show the typical signal-to-noise (SNR) and total harmonic distortion (THD) of the INA851 driving the ADS8900B SAR ADC at full-scale range and at different gain configurations. The RC filter combination (RFIL, CFIL) shown in Figure 9-6 helps attenuate the nonlinear charge kickback of the ADC and optimize for best THD performance. The combination of the RC filter and the feedback capacitor CFB allow for the best trade-off between harmonic distortion and maintaining stability of the FDA. Low voltage-coefficient C0G capacitors are used everywhere in the signal path (CFB, CFIL) for the low-distortion properties.

For other bandwidth requirements, adjust the feedback capacitor accordingly, and verify the circuit performance using a SPICE simulation using the INA851 TINA-TI™ SPICE Model. The amplifier output voltage must settle within the ADC bit accuracy during the ADC acquisition time window. Verify the desired circuit is stable; that is, the FDA has more than a 45º phase margin.

Table 9-2 INA851 + ADS8900B FFT Data Summary
INPUT AMPLITUDE (Vpk) RG RESISTOR (Ω) GIN (V/V) GOUT (V/V) SNR (dB) THD (dB) ENOB (Bits)
23.7378 None 1 0.2 100.7 –117.3 16.42
4.7476 None 1 1 100.6 –122.7 16.41
0.2374 316 20 1 99.1 –112.0 16.10
0.0475 60.4 100 1 91.1 –99.0 14.64
GUID-20221011-SS0I-7SMP-J3VW-KDHFWC7M6LW6-low.png
G = 0.2 V/V, fIN = 1 kHz, SNR = 100.73 dB, THD = –117.28 dB
Figure 9-7 Noise Performance FFT Plots for G = 0.2 V/V
GUID-20221011-SS0I-MTDN-P2R2-XFJGBSCTTFP1-low.png
G = 1 V/V, fIN = 1 kHz, SNR = 100.6 dB, THD = –122.74 dB
Figure 9-8 Noise Performance FFT Plots for G = 1 V/V