SBOS999A March   2022  – October 2022 INA851

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Related Products
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Adjustable Gain Setting
        1. 8.3.1.1 Gain Drift
      2. 8.3.2 Offset Voltage
      3. 8.3.3 Input Common-Mode Range
      4. 8.3.4 Input Protection
      5. 8.3.5 Output Clamping
      6. 8.3.6 Low Noise
    4. 8.4 Device Functional Modes
  9. 9 Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 Output Common-Mode Pin
      2. 9.1.2 Output-Stage Gain Selection and Noise-Gain Shaping
      3. 9.1.3 Input Bias Current Return Path
      4. 9.1.4 Thermal Effects due to Power Dissipation
    2. 9.2 Typical Applications
      1. 9.2.1 Three-Pin Programmable Logic Controller (PLC)
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
        3. 9.2.1.3 Application Curves
      2. 9.2.2 20-Bit, 1-MSPS ADS8900B Driver Circuit With FDA Noise Filter
        1. 9.2.2.1 Design Requirements
        2. 9.2.2.2 Application Curves
      3. 9.2.3 24-Bit, 200 kSPS, Delta-Sigma ADS127L11 ADC Driver Circuit With FDA Noise Filter
        1. 9.2.3.1 Design Requirements
        2. 9.2.3.2 Application Curves
    3. 9.3 Power Supply Recommendations
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
      2. 9.4.2 Layout Example
  10. 10Device and Documentation Support
    1. 10.1 Device Support
      1. 10.1.1 Development Support
        1. 10.1.1.1 PSpice® for TI
        2. 10.1.1.2 TINA-TI™ Simulation Software (Free Download)
    2. 10.2 Documentation Support
      1. 10.2.1 Related Documentation
    3. 10.3 Receiving Notification of Documentation Updates
    4. 10.4 Support Resources
    5. 10.5 Trademarks
    6. 10.6 Electrostatic Discharge Caution
    7. 10.7 Glossary
  11. 11Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

8.3.1 Adjustable Gain Setting

Figure 8-2 shows that the INA851 input-stage gain is set by a single external resistor (RG) connected between the RG pins. The gain of the output stage can be set to a unity gain of 1 V/V by floating the G02+ and G02– pins, or to an attenuating gain of 0.2 V/V by shorting those pins to the respective OUT+ and OUT– pins.

Figure 8-2 Simplified Diagram of the INA851 With Gain Equations

If the output stage is in the unity gain configuration, the value of RG is selected according to the following equation:

Equation 1. G = 1 + 6 k Ω R G

When OUT+ is shorted to G02+ (pin 11 to pin 12) and OUT– is shorted to G02– (pin 9 to pin 10) so that the output stage is in the attenuating configuration, the gain equation becomes:

Equation 2. G = 0.2 × 1 + 6 k Ω R G

Table 8-1 lists several commonly used gains and resistor values, as well as the additional gain error that is contributed by the gain resistors. The 6-kΩ term in the gain equation is a result of the sum of the two internal 3-kΩ feedback resistors. These on-chip resistors are laser-trimmed to accurate absolute values. The accuracy and temperature coefficients of these resistors are included in the gain accuracy and drift specifications of the INA851. The 5-kΩ and 1.25-kΩ resistors used in the output stage are ratiometrically matched to achieve stable 1-V/V and 0.2-V/V gain terms; although, the resistor values can shift up to 15%, depending on production.

Table 8-1 Commonly Used Gains and Resistor Values
DESIRED GAIN
(V/V)		 RG
(Ω)		 NEAREST 1% RG
(Ω)		 CALCULATED GAIN (V/V) CONTRIBUTED GAIN ERROR (%)
0.2 NC, short OUT+ to G02+
and OUT– to G02–		 NC 0.200 N/A
0.5 4 k, short OUT+ to G02+
and OUT– to G02–		 4.02 k 0.499 0.30
1 NC NC 1.000 N/A
2 6 k 5.97 k 2.005 –0.25
5 1.5 k 1.5 k 5.000 0.00
10 666.67 665 10.023 –0.23
20 315.79 316 19.987 0.06
50 122.45 124 49.387 1.23
100 60.61 60.4 100.338 –0.34
200 30.15 30.1 200.336 –0.17
500 12.02 12.1 496.868 0.63
1000 6.01 6.04 994.377 0.56
10000 600 m 604 m 9934.775 0.65

As shown in Figure 8-2 and explained in more detail in Section 9.4, make sure to connect low-ESR, 0.1-µF ceramic bypass capacitors between each supply pin and ground, and to place these capacitors as close as possible to the device pins.