SLLS897F march 2008 – august 2023 ISO1176
PRODUCTION DATA
- 1
- 1 Features
- 2 Applications
- 3 Description
- 4 Revision History
- 5 Pin Configuration and Functions
-
6 Specifications
- 6.1 Absolute Maximum Ratings
- 6.2 ESD Ratings
- 6.3 Recommended Operating Conditions
- 6.4 Thermal Information
- 6.5 Power Ratings
- 6.6 Insulation Specifications
- 6.7 Safety-Related Certifications
- 6.8 Safety Limiting Values
- 6.9 Electrical Characteristics: Driver
- 6.10 Electrical Characteristics: Receiver
- 6.11 Supply Current
- 6.12 Electrical Characteristics: ISODE-Pin
- 6.13 Switching Characteristics: Driver
- 6.14 Switching Characteristics: Receiver
- 6.15 Insulation Characteristics Curves
- 6.16 Typical Characteristics
- 7 Parameter Measurement Information
- 8 Detailed Description
- 9 Application and Implementation
- 10Power Supply Recommendations
- 11Layout
- 12Device and Documentation Support
- 13Mechanical, Packaging, and Orderable Information
Package Options
Mechanical Data (Package|Pins)
- DW|16
Thermal pad, mechanical data (Package|Pins)
Orderable Information
7 Parameter Measurement Information
Figure 7-1 Open
Circuit Voltage Test Circuit
Figure 7-2 VOD Test Circuit
Figure 7-3 Driver
VOD With Common-Mode Loading Test Circuit
Figure 7-4 Driver
VOD and VOC Without Common-Mode Loading Test
Circuit
Figure 7-5 Steady-State Output Voltage Test Circuit and Voltage Waveforms
Figure 7-6 VOD(RING) Waveform and Definitions
Figure 7-7 Input
Voltage Hysteresis Test Circuit
Figure 7-8 Driver
Short-Circuit Test Circuit and Waveforms (Short-Circuit Applied at Time
t=0)
Figure 7-9 IOS(SS) Steady State Short-Circuit Output Current Test
Circuit
Figure 7-10 Driver
Switching Test Circuit and Waveforms
Figure 7-11 Driver
Output Transition Skew Test Circuit and Waveforms
Figure 7-12 Driver
Enable and Disable Test, D at Logic Low Test Circuit and Waveforms
Figure 7-13 Driver
Enable and Disable Test, D at Logic High Test Circuit and Waveforms
Figure 7-14 DE to
ISODE Prop Delay Test Circuit and Waveforms
Figure 7-15 Receiver
DC Parameter Definitions
Figure 7-16 Receiver
Switching Test Circuit and Waveforms
Figure 7-17 Receiver
Enable Test Circuit and Waveforms, Data Output High
Figure 7-18 Receiver
Enable Test Circuit and Waveforms, Data Output Low
Figure 7-19 Common-Mode Rejection Test Circuit
Figure 7-20 Common-Mode Transient Immunity Test Circuit