SLLSF22H April   2018  – June 2024 ISO1410 , ISO1412 , ISO1430 , ISO1432 , ISO1450 , ISO1452

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Description Continued
  6. 5 Device Comparison Table
  7. 6 Pin Configuration and Functions
    1.     Pin Functions: Full-Duplex Device
    2.     Pin Functions: Half-Duplex Device
  8. 7 Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  Recommended Operating Conditions
    4. 7.4  Thermal Information
    5. 7.5  Power Ratings
    6. 7.6  Insulation Specifications
    7. 7.7  Safety-Related Certifications
    8. 7.8  Safety Limiting Values
    9. 7.9  Electrical Characteristics: Driver
    10. 7.10 Electrical Characteristics: Receiver
    11. 7.11 Supply Current Characteristics: Side 1 (ICC1)
    12. 7.12 Supply Current Characteristics: Side 2 (ICC2)
    13. 7.13 Switching Characteristics: Driver
    14. 7.14 Switching Characteristics: Receiver
    15. 7.15 Insulation Characteristics Curves
    16. 7.16 Typical Characteristics
  9. 8 Parameter Measurement Information
  10. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1 Electromagnetic Compatibility (EMC) Considerations
      2. 9.3.2 Failsafe Receiver
      3. 9.3.3 Thermal Shutdown
      4. 9.3.4 Glitch-Free Power Up and Power Down
    4. 9.4 Device Functional Modes
      1. 9.4.1 Device I/O Schematics
  11. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Application
      1. 10.2.1 Design Requirements
      2. 10.2.2 Detailed Design Procedure
        1. 10.2.2.1 Data Rate and Bus Length
        2. 10.2.2.2 Stub Length
        3. 10.2.2.3 Bus Loading
      3. 10.2.3 Application Curves
        1. 10.2.3.1 Insulation Lifetime
  12. 11Power Supply Recommendations
  13. 12Layout
    1. 12.1 Layout Guidelines
      1. 12.1.1 PCB Material
    2. 12.2 Layout Example
  14. 13Device and Documentation Support
    1. 13.1 Documentation Support
      1. 13.1.1 Related Documentation
        1. 13.1.1.1 Related Links
    2. 13.2 Receiving Notification of Documentation Updates
    3. 13.3 Support Resources
    4. 13.4 Trademarks
    5. 13.5 Electrostatic Discharge Caution
    6. 13.6 Glossary
  15. 14Revision History
  16. 15Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • DW|16
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7.6 Insulation Specifications

PARAMETERTEST CONDITIONSSPECIFICATIONSUNIT
DW-16
IEC 60664-1
CLRExternal clearance (1)Side 1 to side 2 distance through air>8mm
CPGExternal creepage (1)Side 1 to side 2 distance across package surface>8mm
DTIDistance through the insulationMinimum internal gap (internal clearance)>17µm
CTIComparative tracking indexIEC 60112; UL 746A>600V
Material GroupAccording to IEC 60664-1I
Overvoltage categoryRated mains voltage ≤ 600 VRMSI-IV
Rated mains voltage ≤ 1000 VRMSI-III
DIN VDE V 0884-11:2017-01(2)
VIORMMaximum repetitive peak isolation voltageAC voltage (bipolar)1500VPK
VIOWMMaximum working isolation voltageAC voltage (sine wave); time-dependent dielectric breakdown (TDDB) test; see Figure 10-71060VRMS
DC voltage1500VDC
VIOTMMaximum transient isolation voltageVTEST = VIOTM , t = 60 s (qualification); VTEST = 1.2 × VIOTM, t = 1 s (100% production)7071VPK
VIOSMMaximum surge isolation voltage
ISO141x (3)		Test method per IEC 62368-1, 1.2/50 µs waveform, VTEST = 1.6 × VIOSM = 10000 VPK (qualification)6250VPK
Maximum surge isolation voltage
ISO141xB (3)		Test method per IEC 62368-1, 1.2/50 µs waveform, VTEST = 1.3 × VIOSM = 6000 VPK (qualification)4615VPK
qpdApparent charge (4)Method a: After I/O safety test subgroup 2/3, Vini = VIOTM, tini = 60 s; Vpd(m) = 1.2 × VIORM , tm = 10 s≤ 5pC
Method a: After environmental tests subgroup 1, Vini = VIOTM, tini = 60 s;
ISO14xx: Vpd(m) = 1.6 × VIORM , tm = 10 s
ISO14xxB: Vpd(m) = 1.2 × VIORM , tm = 10 s		≤ 5
Method b1: At routine test (100% production) and preconditioning (type test), Vini = VIOTM, tini = 1 s;
ISO14xx: Vpd(m) = 1.875 × VIORM , tm = 1 s
ISO14xxB: Vpd(m) = 1.5 × VIORM , tm = 1 s		≤ 5
CIOBarrier capacitance, input to output (5)VIO = 0.4 × sin (2 πft), f = 1 MHz1pF
RIOInsulation resistance, input to output (5)VIO = 500 V,  TA = 25°C> 1012Ω
VIO = 500 V,  100°C ≤ TA ≤ 150°C> 1011
VIO = 500 V at  TS = 150°C> 109
Pollution degree2
Climatic category40/125/21
UL 1577
VISOWithstand isolation voltageVTEST = VISO , t = 60 s (qualification);
VTEST = 1.2 × VISO , t = 1 s (100% production)		5000VRMS
(1) Creepage and clearance requirements should be applied according to the specific equipment isolation standards of an application. Care should be taken to maintain the creepage and clearance distance of a board design to ensure that the mounting pads of the isolator on the printed-circuit board do not reduce this distance. Creepage and clearance on a printed-circuit board become equal in certain cases. Techniques such as inserting grooves, ribs, or both on a printed circuit board are used to help increase these specifications.
(2) ISO14xx is suitable for safe electrical insulation and ISO14xxB is suitable for basic electrical insulation only within the safety ratings. Compliance with the safety ratings shall be ensured by means of suitable protective circuits.
(3) Testing is carried out in air or oil to determine the intrinsic surge immunity of the isolation barrier.
(4) Apparent charge is electrical discharge caused by a partial discharge (pd).
(5) All pins on each side of the barrier tied together creating a two-pin device.