SLLSF22H April   2018  – June 2024 ISO1410 , ISO1412 , ISO1430 , ISO1432 , ISO1450 , ISO1452

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Description Continued
  6. 5 Device Comparison Table
  7. 6 Pin Configuration and Functions
    1.     Pin Functions: Full-Duplex Device
    2.     Pin Functions: Half-Duplex Device
  8. 7 Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  Recommended Operating Conditions
    4. 7.4  Thermal Information
    5. 7.5  Power Ratings
    6. 7.6  Insulation Specifications
    7. 7.7  Safety-Related Certifications
    8. 7.8  Safety Limiting Values
    9. 7.9  Electrical Characteristics: Driver
    10. 7.10 Electrical Characteristics: Receiver
    11. 7.11 Supply Current Characteristics: Side 1 (ICC1)
    12. 7.12 Supply Current Characteristics: Side 2 (ICC2)
    13. 7.13 Switching Characteristics: Driver
    14. 7.14 Switching Characteristics: Receiver
    15. 7.15 Insulation Characteristics Curves
    16. 7.16 Typical Characteristics
  9. 8 Parameter Measurement Information
  10. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1 Electromagnetic Compatibility (EMC) Considerations
      2. 9.3.2 Failsafe Receiver
      3. 9.3.3 Thermal Shutdown
      4. 9.3.4 Glitch-Free Power Up and Power Down
    4. 9.4 Device Functional Modes
      1. 9.4.1 Device I/O Schematics
  11. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Application
      1. 10.2.1 Design Requirements
      2. 10.2.2 Detailed Design Procedure
        1. 10.2.2.1 Data Rate and Bus Length
        2. 10.2.2.2 Stub Length
        3. 10.2.2.3 Bus Loading
      3. 10.2.3 Application Curves
        1. 10.2.3.1 Insulation Lifetime
  12. 11Power Supply Recommendations
  13. 12Layout
    1. 12.1 Layout Guidelines
      1. 12.1.1 PCB Material
    2. 12.2 Layout Example
  14. 13Device and Documentation Support
    1. 13.1 Documentation Support
      1. 13.1.1 Related Documentation
        1. 13.1.1.1 Related Links
    2. 13.2 Receiving Notification of Documentation Updates
    3. 13.3 Support Resources
    4. 13.4 Trademarks
    5. 13.5 Electrostatic Discharge Caution
    6. 13.6 Glossary
  15. 14Revision History
  16. 15Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • DW|16
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7.13 Switching Characteristics: Driver

All typical specs are at VCC1=3.3V, VCC2=5V, TA=27°C, (Min/Max specs are over recommended operating conditions unless otherwise noted)
PARAMETERTEST CONDITIONSMINTYPMAXUNIT
500-kbps DEVICES
tr, tfDifferential output rise time and fall timeRL = 54 Ω, CL = 50 pF, see Figure 8-3240460680ns
tPHL, tPLHPropagation delayRL = 54 Ω, CL = 50 pF, see Figure 8-3310570ns
PWDPulse width distortion(1), |tPHL – tPLH|RL = 54 Ω, CL = 50 pF, see Figure 8-3450ns
tPHZ, tPLZDisable timeSee Figure 8-6, and Figure 8-7125200ns
tPZH, tPZLEnable timeSee Figure 8-6, and Figure 8-7160600ns
12-Mbps DEVICES
tr, tfDifferential output rise time and fall timeRL = 54 Ω, CL = 50 pF, VCC2= 4.5 V to 5.5 V, see Figure 8-31025ns
RL = 54 Ω, CL = 50 pF, VCC2= 3 V to 3.6 V, see Figure 8-327.8ns
tPHL, tPLHPropagation delayRL = 54 Ω, CL = 50 pF, see Figure 8-368125ns
PWDPulse width distortion(1), |tPHL – tPLH|RL = 54 Ω, CL = 50 pF, see Figure 8-3210ns
tPHZ, tPLZDisable timeSee Figure 8-6, and Figure 8-775125ns
tPZH, tPZLEnable timeSee Figure 8-6, and Figure 8-775160ns
50-Mbps DEVICES
tr, tfDifferential output rise time and fall timeRL = 54 Ω, CL = 50 pF, VCC2= 4.5 V to 5.5 V, see Figure 8-34.76ns
RL = 54 Ω, CL = 50 pF, VCC2= 3 V to 3.6 V, see Figure 8-37.8ns
tPHL, tPLHPropagation delayRL = 54 Ω, CL = 50 pF, see Figure 8-31941ns
PWDPulse width distortion(1), |tPHL – tPLH|RL = 54 Ω, CL = 50 pF, see Figure 8-316ns
tPHZ, tPLZDisable timeSee Figure 8-6, and Figure 8-72546ns
tPZH, tPZLEnable timeSee Figure 8-6, and Figure 8-73278ns
(1) Also known as pulse skew.