The ISO1500 device is a galvanically-isolated differential line transceiver for TIA/EIA RS-485 and RS-422 applications. This device has a 3-channel digital isolator and an RS-485 transceiver in an ultra-small 16-pin SSOP package. The bus pins of this transceiver are protected against IEC ESD contact discharge and IEC EFT events. The receiver output has a failsafe for bus open, short, and idle conditions. The small solution size of ISO1500 greatly reduces the board space required compared to other integrated isolated RS-485 solutions or discrete implementation with optocouplers and non-isolated RS-485 transceiver.
The device is used for long distance communications. Isolation breaks the ground loop between the communicating nodes, allowing for a much larger common mode voltage range. The symmetrical isolation barrier of each device is tested to provide 3000 VRMS of isolation for 1 minute per UL 1577 between the bus-line transceiver and the logic-level interface.
The ISO1500 device can operate from 1.71 V to 5.5 V on side 1 which lets the devices interface with low-voltage FPGAs and ASICs. The supply voltage on side 2 is from 4.5 V to 5.5 V. This device supports a wide operating ambient temperature range from –40°C to +125°C.
PART NUMBER | PACKAGE | BODY SIZE (NOM) |
---|---|---|
ISO1500 | SSOP (16) | 4.90 mm × 3.90 mm |
Changes from C Revision (September 2019) to D Revision
Changes from B Revision (May 2019) to C Revision
Changes from A Revision (December 2018) to B Revision
Changes from * Revision (September 2018) to A Revision
PIN | I/O | DESCRIPTION | |
---|---|---|---|
NAME | NO. | ||
A | 12 | I/O | Transceiver noninverting input or output (I/O) on the bus side |
B | 13 | I/O | Transceiver inverting input or output (I/O) on the bus side |
D | 6 | I | Driver input |
DE | 5 | I | Driver enable. This pin enables the driver output when high and disables the driver output when low or open. |
GND1 | 2 | — | Ground connection for VCC1 |
8 | |||
GND2 | 9 | — | Ground connection for VCC2 |
15 | |||
NC(1) | 7 | — | No internal connection |
11 | |||
14 | |||
R | 3 | O | Receiver output |
RE | 4 | I | Receiver enable. This pin disables the receiver output when high or open and enables the receiver output when low. |
VCC1 | 1 | — | Logic-side power supply |
VCC2 | 10 | — | Transceiver-side power supply. These pins are not connected internally and must be shorted externally on PCB. |
16 |
MIN | MAX | UNIT | ||
---|---|---|---|---|
VCC1 | Supply voltage, side 1 | -0.5 | 6 | V |
VCC2 | Supply voltage, side 2 | -0.5 | 6 | V |
VIO | Logic voltage level (D, DE, RE, R) | -0.5 | VCC1+0.5(3) | V |
IO | Output current on R pin | -15 | 15 | mA |
VBUS | Voltage on bus pins (A, B, Y, Z w.r.t GND2) | -18 | 18 | V |
TJ | Junction temperature | -40 | 150 | ℃ |
TSTG | Storage temperature | -65 | 150 | ℃ |
VALUE | UNIT | |||
---|---|---|---|---|
V(ESD) | Electrostatic discharge
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001 |
All pins except bus pins(1) | ±4000 | V |
Bus terminals to GND2(1) | ±16000 | V | ||
Electrostatic discharge
Charged device model (CDM), per JEDEC specification JESD22-C101 |
All pins(2) | ±1500 |
MIN | MAX | UNIT | ||
---|---|---|---|---|
VCC1 | Supply Voltage, Side 1, 1.8-V operation | 1.71 | 1.89 | V |
Supply Voltage, Side 1, 2.5-V, 3.3-V and 5.5-V operation | 2.25 | 5.5 | V | |
VCC2 | Supply Voltage, Side 2 | 4.5 | 5.5 | V |
VI | Common mode voltage at any bus terminal: A or B | -7 | 12 | V |
VIH | High-level input voltage (D, DE, RE inputs) | 0.7*VCC1 | VCC1 | V |
VIL | Low-level input voltage (D, DE, RE inputs) | 0 | 0.3*VCC1 | V |
VID | Differential input voltage | -12 | 12 | V |
IO | Output current, Driver | -60 | 60 | mA |
IOR | Output current, Receiver | -4 | 4 | mA |
RL | Differential load resistance | 54 | Ω | |
1/tUI | Signaling rate | 1 | Mbps | |
TA | Operating ambient temperature | -40 | 125 | °C |
THERMAL METRIC(1) | ISO1500 | UNIT | |
---|---|---|---|
DBQ (SSOP) | |||
16 PINS | |||
RθJA | Junction-to-ambient thermal resistance | 112.7 | °C/W |
RθJC(top) | Junction-to-case (top) thermal resistance | 57.2 | °C/W |
RθJB | Junction-to-board thermal resistance | 64.0 | °C/W |
ΨJT | Junction-to-top characterization parameter | 32.1 | °C/W |
ΨJB | Junction-to-board characterization parameter | 63.7 | °C/W |
RθJC(bot) | Junction-to-case (bottom) thermal resistance | -- | °C/W |
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
---|---|---|---|---|---|---|
PD | Maximum power dissipation (both sides) | VCC1 = VCC2 = 5.5 V, TA=125°C, TJ = 150°C, A-B load = 54 Ω ||50pF, Load on R=15pF
Input a 500kHz 50% duty cycle square wave to D pin with VDE=VCC1, VRE=GND1 |
278 | mW | ||
PD1 | Maximum power dissipation (side-1) | 28 | mW | |||
PD2 | Maximum power dissipation (side-2) | 250 | mW |
PARAMETER | TEST CONDITIONS | SPECIFICATIONS | UNIT | |
---|---|---|---|---|
DBQ-16 | ||||
IEC 60664-1 | ||||
CLR | External clearance (1) | Side 1 to side 2 distance through air | >3.7 | mm |
CPG | External creepage (1) | Side 1 to side 2 distance across package surface | >3.7 | mm |
DTI | Distance through the insulation | Minimum internal gap (internal clearance) | >17 | µm |
CTI | Comparative tracking index | IEC 60112; UL 746A | >600 | V |
Material Group | According to IEC 60664-1 | I | ||
Overvoltage category | Rated mains voltage ≤ 300 VRMS | I-III | ||
DIN VDE V 0884-11:2017-01(2) | ||||
VIORM | Maximum repetitive peak isolation voltage | AC voltage (bipolar) | 566 | VPK |
VIOWM | Maximum isolation working voltage | AC voltage (sine wave); time-dependent dielectric breakdown (TDDB) test; | 400 | VRMS |
DC voltage | 566 | VDC | ||
VIOTM | Maximum transient isolation voltage | VTEST = VIOTM , t = 60 s (qualification); VTEST = 1.2 × VIOTM, t = 1 s (100% production) | 4242 | VPK |
VIOSM | Maximum surge isolation voltage
ISO1500 (3) |
Test method per IEC 62368-1, 1.2/50 µs waveform, VTEST = 10000 VPK (qualification) | 4000 | VPK |
qpd | Apparent charge (4) | Method a: After I/O safety test subgroup 2/3, Vini = VIOTM, tini = 60 s; Vpd(m) = 1.2 × VIORM , tm = 10 s | ≤ 5 | pC |
Method a: After environmental tests subgroup 1, Vini = VIOTM, tini = 60 s;
Vpd(m) = 1.6 × VIORM , tm = 10 s |
≤ 5 | |||
Method b1: At routine test (100% production) and preconditioning (type test), Vini = VIOTM, tini = 1 s;
Vpd(m) = 1.875 × VIORM , tm = 1 s |
≤ 5 | |||
CIO | Barrier capacitance, input to output (5) | VIO = 0.4 × sin (2 πft), f = 1 MHz | ~1 | pF |
RIO | Insulation resistance, input to output (5) | VIO = 500 V, TA = 25°C | > 1012 | Ω |
VIO = 500 V, 100°C ≤ TA ≤ 150°C | > 1011 | |||
VIO = 500 V at TS = 150°C | > 109 | |||
Pollution degree | 2 | |||
Climatic category | 40/125/21 | |||
UL 1577 | ||||
VISO | Withstand isolation voltage | VTEST = VISO , t = 60 s (qualification); VTEST = 1.2 × VISO , t = 1 s (100% production) | 3000 | VRMS |
VDE | CSA | UL | CQC | TUV |
---|---|---|---|---|
Certified according to DIN VDE V 0884-11:2017- 01 | Certified according to IEC 60950-1, IEC 62368-1 | Recognized under UL 1577 Component Recognition Program | Certified according to GB4943.1-2011 | Certified according to EN 61010-1:2010/A1:2019, EN 60950-1:2006/A2:2013 and EN 62368-1:2014 |
Maximum transient isolation voltage,
4242 VPK; Maximum repetitive peak isolation voltage, 566 VPK; Maximum surge isolation voltage, 4000 VPK |
CSA 60950-1-07+A1+A2, IEC 60950-1 2nd Ed.+A1+A2, CSA 62368-1-14, and IEC 62368-1 2nd Ed., for pollution degree 2, material group I: 370 VRMS
|
Single protection,
3000 VRMS |
Basic insulation, Altitude ≤ 5000 m, Tropical Climate,
400 VRMS maximum working voltage |
EN 61010-1:2010/A1:2019,
300 VRMS basic isolation ---------------- EN 60950-1:2006/A2:2013 and EN 62368-1:2014, 400 VRMS basic isolation |
Certificate number: 40040142 | Master contract number:
220991 |
File number: E181974 | Certificate number: CQC18001199097 | Client ID number: 77311 |
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
---|---|---|---|---|---|---|
DBQ-16 PACKAGE | ||||||
IS | Safety input, output, or supply current | RθJA = 67.9°C/W, VI = 5.5 V, TJ = 150°C, TA = 25°C, see Figure 1 | 201 | mA | ||
RθJA = 67.9°C/W, VI = 3.6 V, TJ = 150°C, TA = 25°C, see Figure 1 | 308 | |||||
RθJA = 67.9°C/W, VI = 2.75 V, TJ = 150°C, TA = 25°C, see Figure 1 | 403 | |||||
RθJA = 67.9°C/W, VI = 1.89 V, TJ = 150°C, TA = 25°C, see Figure 1 | 586 | |||||
PS | Safety input, output, or total power | RθJA = 67.9°C/W, TJ = 150°C, TA = 25°C, see Figure 2 | 1105 | mW | ||
TS | Maximum safety temperature | 150 | °C |
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
---|---|---|---|---|---|---|
|VOD| | Driver differential-output voltage magnitude | Open circuit voltage, unloaded bus,
4.5 V ≤ VCC2 ≤ 5.5 V |
1.5 | 4.3 | VCC2 | V |
RL = 60 Ω, –7 V ≤ VTEST ≤ 12 V,
4.5 V < VCC2 < 5.5 V (see Figure 19) |
1.5 | 2.5 | V | |||
RL = 100 Ω (see Figure 20), RS-422 load | 2 | 2.9 | V | |||
RL = 54 Ω (see Figure 20), RS-485 load,
4.5 V < VCC2 < 5.5 V |
1.5 | 2.5 | V | |||
Δ|VOD| | Change in differential output voltage between two states | RL = 54 Ω or RL = 100 Ω, see Figure 20 | –50 | 50 | mV | |
VOC | Common-mode output voltage | RL = 54 Ω or RL = 100 Ω, see Figure 20 | 0.5 × VCC2 | 3 | V | |
ΔVOC(SS) | change in steady-state common-mode output voltage between two states | RL = 54 Ω or RL = 100 Ω, see Figure 20 | –50 | 50 | mV | |
VOC(PP) | Peak-to-peak common-mode output voltage | RL = 54 Ω or RL = 100 Ω, see Figure 20 | 300 | mV | ||
IOS | Short-circuit output current | VD = VCC1 or VD = VGND1, VDE = VCC1,
–7 V ≤ VO ≤ 12 V, see Figure 28 |
–175 | 175 | mA | |
Ii | Input current | VD and VDE = 0 V or VD and VDE = VCC1 | –10 | 10 | µA | |
CMTI | Common-mode transient immunity | VD= VCC1 or GND1, VCM = 1200V, See Figure 22 | 85 | 100 | kV/µs |
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
---|---|---|---|---|---|---|
Ii1 | Bus input current | VDE = 0 V, VCC2 = 0 V or VCC2 = 5.5 V, One bus input at –7 V or 12 V, other input at 0 V | –100 | 100 | µA | |
VTH+ | Positive-going input threshold voltage | –7 V ≤ Common mode voltage on bus terminals ≤ 12 V | See (1) | –100 | –50 | mV |
VTH– | Negative-going input threshold voltage | –7 V ≤ Common mode voltage on bus terminals ≤ 12 V | –200 | –145 | See (1) | mV |
Vhys | Input hysteresis (VTH+ – VTH–) | –7 V ≤ Common mode voltage on bus terminals ≤ 12 V | 20 | 45 | mV | |
VOH | Output high voltage on the R pin | VCC1=5V+/-10%, IOH = –4 mA, VID = 200 mV | VCC1 – 0.4 | V | ||
VCC1=3.3V+/-10%, IOH = –2 mA, VID = 200 mV | VCC1 – 0.3 | V | ||||
VCC1=2.5V+/-10%, 1.8V+/-5%, IOH = –1 mA, VID = 200 mV | VCC1 – 0.2 | V | ||||
VOL | Output low voltage on the R pin | VCC1=5V+/-10%, IOL = 4 mA, VID = –200 mV | 0.4 | V | ||
VCC1=3.3V+/-10%, IOL = 2 mA, VID = –200 mV | 0.3 | V | ||||
VCC1=2.5V+/-10%, 1.8V+/-5%, IOL = 1 mA, VID = –200 mV | 0.2 | V | ||||
IOZ | Output high-impedance current on the R pin | VR = 0 V or VR = VCC1, VRE = VCC1 | –1 | 1 | µA | |
Ii | Input current on the RE pin | VRE = 0 V or VRE = VCC1 | –10 | 10 | µA | |
CMTI | Common-mode transient immunity | VID = 1.5 V or -1.5 V, VCM= 1200 V , See Figure 22 | 85 | 100 | kV/µs |
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT |
---|---|---|---|---|---|
DRIVER ENABLED, RECEIVER DISABLED | |||||
Logic-side supply current | VD = VCC1, VCC1 = 5 V ± 10% | 2.6 | 4.4 | mA | |
Logic-side supply current | VD = VCC1, VCC1 = 3.3 V ± 10% | 2.6 | 4.4 | mA | |
Logic-side supply current | D = 1Mbps square wave with 50% duty cycle, VCC1 = 5 V ± 10% | 3.2 | 5.1 | mA | |
Logic-side supply current | D = 1Mbps square wave with 50% duty cycle, VCC1 = 3.3 V ± 10% | 3.2 | 5.1 | mA | |
DRIVER ENABLED, RECEIVER ENABLED | |||||
Logic-side supply current | VRE = VGND1, VD = VCC1, VCC1 = 5 V ± 10% | 2.6 | 4.4 | mA | |
Logic-side supply current | VRE = VGND1, VD = VCC1, VCC1 = 3.3 V ± 10% | 2.6 | 4.4 | mA | |
Logic-side supply current | VRE = VGND1, D = 1Mbps square wave with 50% duty cycle, VCC1 = 5 V ± 10%, CL(R)(1) = 15 pF | 3.4 | 5.2 | mA | |
Logic-side supply current | VRE = VGND1, D= 1Mbps square wave with 50% duty cycle, VCC1 = 3.3 V ± 10%, CL(R)(1) = 15 pF | 3.2 | 5.2 | mA | |
DRIVER DISABLED, RECEIVER ENABLED | |||||
Logic-side supply current | V(A-B) ≥ 200 mV, VD = VCC1, VCC1 = 5 V ± 10% | 1.5 | 3.1 | mA | |
Logic-side supply current | V(A-B) ≥ 200 mV, VD = VCC1, VCC1 = 3.3 V ± 10% | 1.5 | 3.1 | mA | |
Logic-side supply current | (A-B) =1Mbps square wave with 50% duty cycle, VD = VCC1, VCC1 = 5 V ± 10%, CL(R)(1) = 15 pF | 1.7 | 3.2 | mA | |
Logic-side supply current | (A-B) = 1Mbps square wave with 50% duty cycle, VD = VCC1, VCC1 = 3.3 V ± 10%, CL(R)(1) = 15 pF | 1.7 | 3.2 | mA | |
DRIVER DISABLED, RECEIVER DISABLED | |||||
Logic-side supply current | VDE = VGND1, VD = VCC1, VCC1 = 5 V ± 10% | 1.5 | 3.1 | mA | |
Logic-side supply current | VDE = VGND1, VD = VCC1, VCC1 = 3.3 V ± 10% | 1.5 | 3.1 | mA |
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT |
---|---|---|---|---|---|
DRIVER ENABLED, BUS UNLOADED | |||||
Bus-side supply current | VD = VCC1, VCC2 = 5 V ± 10% | 2.5 | 4.4 | mA | |
DRIVER ENABLED, BUS LOADED | |||||
Bus-side supply current | VD = VCC1, RL = 54 Ω, VCC2 = 5 V ± 10% | 52 | 70 | mA | |
Bus-side supply current | D =1Mbps square wave with 50% duty cycle, RL = 54 Ω, CL = 50 pF, VCC2 = 5 V ± 10% | 60 | 80 | mA | |
DRIVER DISABLED, BUS LOADED OR UNLOADED | |||||
Bus-side supply current | VD = VCC1, VCC2 = 5 V ± 10% | 2.4 | 3.9 | mA |
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
---|---|---|---|---|---|---|
1Mbps DEVICE | ||||||
tr, tf | Differential output rise time and fall time | RL = 54 Ω, CL = 50 pF, see Figure 21 | 210 | 300 | ns | |
tPHL, tPLH | Propagation delay | RL = 54 Ω, CL = 50 pF, see Figure 21 | 210 | 300 | ns | |
PWD | Pulse width distortion(1), |tPHL – tPLH| | RL = 54 Ω, CL = 50 pF, see Figure 21 | 3 | 30 | ns | |
tPHZ, tPLZ | Disable time | See Figure 23, and Figure 24 | 160 | 250 | ns | |
tPZH, tPZL | Enable time | See Figure 23, and Figure 24 | 200 | 400 | ns |
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
---|---|---|---|---|---|---|
1Mbps DEVICE | ||||||
tr, tf | Differential output rise time and fall time | CL = 15 pF, see Figure 25 | 2.4 | 4 | ns | |
tPHL, tPLH | Propagation delay | CL = 15 pF, see Figure 25 | 120 | 180 | ns | |
PWD | Pulse width distortion(1), |tPHL – tPLH| | CL = 15 pF, see Figure 25 | 5 | 20 | ns | |
tPHZ, tPLZ | Disable time | See Figure 26 and Figure 27 | 11 | 30 | ns | |
tPZH, tPZL | Enable time | See Figure 26 and Figure 27 | 7 | 20 | ns |
TA = 25°C | DE = VCC1 | RE = GND1 |
TA = 25°C | DE = VCC1 | RE = GND1 |
Driver load = 120 ohm || 50 pF | Load on R = 15 pF | |
DE = VCC1 | D = GND1 | VCC1 = 3.3 V |
VCC2 = 5 V | TA = 25°C | |
TA = 25°C | RL = 54 ohm | DE = D = VCC1 |
VCC1 = 3.3 V | VCC2 = 5 V | |
TA = 25°C | ||
VCC1 = 3.3 V | VCC2 = 5 V | DE = VCC1 |
TA = 25°C | ||
TA = 25°C | DE = VCC1 | RE = GND1 |
Driver load = 54 ohm || 50 pF | Load on R = 15 pF |
DE = VCC1 | D = GND1 | VCC1 = 3.3 V |
VCC2 = 5 V | TA = 25°C | |
VCC1 = 3.3 V | VCC2 = 5 V | |
TA = 25°C | ||
VCC1 = 3.3 V | VCC2 = 5 V | |
VCC1 = 3.3 V | VCC2 = 5 V | TA = 25°C, |
DE = GND1 | RE = GND1 | |
The ISO1500 device is an isolated RS-485/RS-422 transceiver designed to operate in harsh industrial environments. This device supports data transmissions up to 1 Mbps. The ISO1500 device has a 3-channel digital isolator and an RS-485 transceiver in an ultra-small SSOP package. The silicon-dioxide based capacitive isolation barrier supports an isolation withstand voltage of 3 kVRMS and an isolation working voltage of 566 VPK. Isolation breaks the ground loop between the communicating nodes and lets data transfer in the presence of large ground potential differences. The wide logic supply of the device (VCC1) supports interfacing with 1.8-V, 2.5-V, 3.3-V. and 5-V control logic. Functional Block Diagram shows the functional block diagram of the the half-duplex device.
Table 1 shows an overview of the device features.
PART NUMBER | ISOLATION | DUPLEX | DATA RATE | PACKAGE |
---|---|---|---|---|
ISO1500 | Basic | Half | 1 Mbps | 16-pin SSOP |
Many applications in harsh industrial environment are sensitive to disturbances such as electrostatic discharge (ESD), electrical fast transient (EFT), surge and electromagnetic emissions. These electromagnetic disturbances are regulated by international standards such as IEC 61000-4-x and CISPR 22. Although system-level performance and reliability depends, to a large extent, on the application board design and layout, the ISO1500 device has dedicated circuitry to help protect the transceiver from Contact ESD per IEC61000-4-2.
The differential receiver of the ISO1500 device has failsafe protection from invalid bus states caused by:
The differential input of the RS-485 receiver is 0 in any of these conditions for a terminated transmission line. The receiver outputs a failsafe logic-high state so that the output of the receiver is not indeterminate.
The receiver thresholds are offset in the receiver failsafe protection so that the indeterminate range of the input does not include a 0 V differential. The receiver output must generate a logic high when the differential input (VID) is greater than 200 mV to comply with the RS-485 standard. The receiver output must also generate a output a logic low when VID is less than –200 mV to comply with the RS-485 standard. The receiver parameters that determine the failsafe performance are VTH+, VTH–, and VHYS. Differential signals less than –200 mV always cause a low receiver output as shown in the Electrical Characteristics table. Differential signals greater than 200 mV always cause a high receiver output. A differential input signal that is near zero is still greater than the VTH+ threshold which makes the receiver output logic high. The receiver output goes to a low state only when the differential input decreases by VHYS to less than VTH+.
The internal failsafe biasing feature removes the need for the two external resistors that are typically required with traditional isolated RS-485 transceivers as shown in Figure 29.
The ISO1500 device has a thermal shutdown circuit to protect against damage when a fault condition occurs. A driver output short circuit or bus contention condition can cause the driver current to increase significantly which increases the power dissipation inside the device. An increase in the die temperature is monitored and the device is disabled when the die temperature becomes 170℃ (typical) which lets the device decrease the temperature. The device is enabled when the junction temperature becomes 163℃ (typical).
Communication on the bus that already exist between a master node and slave node in an RS485 network must not be disturbed when a new node is swapped in or out of the network. No glitches on the bus occur when the device is:
The ISO1500 device does not cause any false data toggling on the bus when powered up or powered down in a disabled state with supply ramp rates from 100 µs to 10 ms.
Table 2 shows the driver functional modes.
VCC1 | VCC2 | INPUT D | DRIVER ENABLE DE | OUTPUTS | |
---|---|---|---|---|---|
A | B | ||||
PU | PU | H | H | H | L |
L | H | L | H | ||
X | L | Hi-Z | Hi-Z | ||
X | Open | Hi-Z | Hi-Z | ||
Open | H | H | L | ||
PD(2) | PU | X | X | Hi-Z | Hi-Z |
X | PD | X | X | Hi-Z | Hi-Z |
When the driver enable pin, DE, is logic high, the differential outputs, A and B, follow the logic states at data input, D. A logic high at the D input causes the A output to go high and the B output to go low. Therefore the differential output voltage defined by Equation 1 is positive.
A logic low at the D input causes the B output to go high and the A output to go low. Therefore the differential output voltage defined by Equation 1 is negative. A logic low at the DE input causes both outputs to go to the high-impedance (Hi-Z) state. The logic state at the D pin is irrelevant when the DE input is logic low. The DE pin has an internal pulldown resistor to ground. The driver is disabled (bus outputs are in the Hi-Z) by default when the DE pin is left open. The D pin has an internal pullup resistor. The A output goes high and the B output goes low when the D pin is left open while the driver enabled.
Table 3 shows the receiver functional modes.
VCC1 | VCC2 | DIFFERENTIAL INPUT | RECEIVER ENABLE RE | OUTPUT R |
---|---|---|---|---|
VID = VA – VB | ||||
PU | PU | –0.02 V ≤ VID | L | H |
–0.2 V < VID < 0.02 V | L | Indeterminate | ||
VID≤ –0.2 V | L | L | ||
X | H | Hi-Z | ||
X | Open | Hi-Z | ||
Open, Short, Idle | L | H | ||
PD(2) | PU | X | X | Hi-Z |
PU | PD | X | L | H |
PD(2) | PD | X | X | Hi-Z |
The receiver is enabled when the receiver enable pin, RE, is logic low. The receiver output, R, goes high when the differential input voltage defined by Equation 2 is greater than the positive input threshold, VTH+.
The receiver output, R, goes low when the differential input voltage defined by Equation 2 is less than the negative input threshold, VTH–. If the VID voltage is between the VTH+ and VTH– thresholds, the output is indeterminate. The receiver output is in the Hi-Z state and the magnitude and polarity of VID are irrelevant when the RE pin is logic high or left open. The internal biasing of the receiver inputs causes the output to go to a failsafe-high when the transceiver is disconnected from the bus (open-circuit), the bus lines are shorted to one another (short-circuit), or the bus is not actively driven (idle bus).
NOTE
Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality.
The ISO1500 device is designed for bidirectional data transfer on multipoint RS-485 networks. The design of each RS-485 node in the network requires an ISO1500 device and an isolated power supply as shown in Figure 32.
An RS-485 bus has multiple transceivers that connect in parallel to a bus cable. Both cable ends are terminated with a termination resistor, RT, to remove line reflections. The value of RT matches the characteristic impedance, Z0, of the cable. This method, known as parallel termination, lets higher data rates be used over a longer cable length.
In half-duplex implementation, as shown in Figure 31, the driver and receiver enable pins let any node at any given moment be configured in either transmit or receive mode which decreases cable requirements.
Figure 32 shows the application circuit of the ISO1500 device.
Unlike an optocoupler-based solution, which requires several external components to improve performance, provide bias, or limit current, the ISO1500 device only requires external bypass capacitors to operate.
The RS-485 bus is a robust electrical interface suitable for long-distance communications. The RS-485 interface can be used in a wide range of applications with varying requirements of distance of communication, data rate, and number of nodes.
The RS-485 standard has typical curves similar to those shown in Figure 33. These curves show the inverse relationship between signaling rate and cable length. If the data rate of the payload between two nodes is lower, the cable length between the nodes can be longer.
Applications can increase the cable length at slower data rates compared to what is shown in Figure 33 by allowing for jitter of 5% or higher. Use Figure 33 as a guideline for cable selection, data rate, cable length and subsequent jitter budgeting.
In an RS-485 network, the distance between the transceiver inputs and the cable trunk is known as the stub. The stub should be as short as possible when a node is connected to the bus. Stubs are a non-terminated piece of bus line that can introduce reflections of varying phase as the length of the stub increases. The electrical length, or round-trip delay, of a stub should be less than one-tenth of the rise time of the driver as a general guideline. Therefore, the maximum physical stub length (L(STUB)) is calculated as shown in Equation 3.
where
The current supplied by the driver must supply into a load because the output of the driver depends on this current. Add transceivers to the bus to increase the total bus loading. The RS-485 standard specifies a hypothetical term of a unit load (UL) to estimate the maximum number of possible bus loads. The UL represents a load impedance of approximately 12 kΩ. Standard-compliant drivers must be able to drive 32 of these ULs.
The ISO1500 device has 1/8 UL impedance transceiver and can connect up to 256 nodes to the bus.
To make sure device operation is reliable at all data rates and supply voltages, a 0.1-μF bypass capacitor is recommended at the logic and transceiver supply pins (VCC1 and VCC2). The capacitors should be placed as near to the supply pins as possible. Side 2 requires one VCC2 decoupling capacitor on each VCC2 pin. If only one primary-side power supply is available in an application, isolated power can be generated for the secondary-side with the help of a transformer driver such as TI's SN6505B device. For such applications, detailed power supply design and transformer selection recommendations are available in the SN6505 Low-Noise 1-A Transformer Drivers for Isolated Power Supplies data sheet.